Overview

This chipset is identical to the TOPCAT Cached 286/386sx PC/AT-Compatible Chip Set chipset, but without the VL82C325 Cache Controller.

The TOPCAT 286/386SX chip set from VLSI Technology, Inc. is a very high-integration chip set for use in the design of PC/AT-compatible based systems. This chip set is intended for use in 80286 or 80386SX microprocessor-based systems with clock speeds from 12 to 25 MHz.

The TOPCAT 286/386SX chip set provides design engineers with a very flexible, high- performance, low-cost board design solution for IBM PC/AT-compatible desktop, laptop, portable, and hand-held computers.

The TOPCAT 286/386SX two-device chip set has been designed with the highest integration consistent with economic and reliable system design. It provides a complete board design using only four non-memory devices including the microprocessor.

VLSI's TOPCAT 286/386SX chip set was designed with seven goals.

• Lowest system board cost
• Smallest board area requirement
• Highest performance in both cached and non-cached systems
• Single board design for:
  • 12 to 15 MHz operation
  • Cache or non-cache
  • 512K byte to 32M byte memory using 256K, 1M and 4M bit DRAM
  • Laptop or desktop applications
• Full hardware LIM EMS 4.0 support for highest possible performance
• Built-in, in-circuit test modes for easy board level testing
• The VL82C320A interfaces to the VL82C335 "look-aside" Cache Controller

With VLSI's TOPCAT 286/386SX chip set, you can be assured that your high-performance system design needs are met.

• Two-chip, PC/AT-compatible chip set capable of use in 80286-based systems up to 20 MHz or in 80386SX-based systems up to 25 MHz
• Two 160-lead plastic quad flatpacks, 1.0 and 1.5 micron CMOS
• Memory control of one to four banks of 16-bit DRAM using 256K, 1M, or 4M components allowing 32M bytes on system board
• Two-/four-way page mode interleaving or direct access on system board memory
• Programmable DRAM timing parameters
• Remap option allows logical reordering of system board DRAM banks
• Staggered system board refresh optionally decoupled from slot bus refresh
• Built-in "sleep" mode features, including use of slow refresh DRAMs in power critical operations
• Hardware supports full LIM EMS 4.0 spec over entire 32M bye memory map
• DMA expanded to allow transfers over 32M byte range
• Shadow RAM support in 16K increments.
• Support for 80287 or 80387SX numerical coprocessors
• Internal switching and programmable CPU clock support for PC/AT-compatible and "turbo" modes
• Asynchronous or synchronous slot bus with "Bus Quiet" mode
• Build-in real-time clock and scratchpad RAM
• Additional 64 bytes of battery backed RAM in RTC
• Supports 8- or 16-bit wide BIOS ROMs
• In-circuit test modes
• Support for the VL82C335 Cache Controller is provided by the VL82C320A