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Chip family#332(Steamroller) has been deleted by Wolt1x -
Chip family#330(K10 - A4 series) has been deleted by Wolt1x -
Chip family#218(K7 - Model 4 Athlon (Thunderbird)) has been dissociated fromChip family#215(K7 - Model 3 Duron (Spitfire)) by computerguy096 -
Chip family#218has been updated by computerguy096Attribute Old value New value miscSpecsMicroarchitecture: CPUID: 0: 642 (model 4)<br/>1: 644 (model 4)<br/><br/>L1... Microarchitecture: CPUID: 642 (model 4),644 (model 4)<br/>L1 cache: 64KB co... -
Chip family#143has been updated by Wolt1xAttribute Old value New value miscSpecsMicroarchitecture: CPUID:
Process node:
Microarchitecture: CPUID:
Process node:
nameCore i7 (Westmere) Core i7 (Westmere 1366) -
Chip family#348has been updated by Wolt1xAttribute Old value New value nameCore i3/5/7 (Broadwell) Core i5/7 (Broadwell) -
Chip family#348has been inserted by Wolt1xAttribute Old value New value idnull 348 miscSpecsnull namenull Core i3/5/7 (Broadwell) -
Chip family#312has been updated by Wolt1xAttribute Old value New value descriptionnull Socket LGA1356 Pentium Family miscSpecsMicroarchitecture: CPUID:
Process node: 32nm
Microarchitecture: CPUID:
Process node: 32nm
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Chip family#311has been updated by Wolt1xAttribute Old value New value descriptionnull Socket LGA1356 Xeon E5 Family miscSpecsMicroarchitecture: CPUID:
Process node: 32nm
Microarchitecture: CPUID:
Process node: 32nm
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Chip family#26(Pentium (P5)) has been associated toEntity documentation#219(Pentium 60/66 datasheet (241595-002) [1994-11]) by computerguy096 -
Chip family#26has been updated by computerguy096Attribute Old value New value miscSpecsMicroarchitecture: CPUID: 0: 513 (B1)<br/>1: 515 (C1)<br/>2: 517 (D1)<br/>3... Microarchitecture: CPUID: 513 (B1),515 (C1),517 (D1),51A (tA1)<br/>L1 cache... -
Chip family#150has been updated by Wolt1xAttribute Old value New value nameCore i3/5/7 & Xeon E3 v6 (Kaby Lake) Core i3/5/7 (Kaby Lake) -
Chip family#150has been updated by Wolt1xAttribute Old value New value miscSpecsMicroarchitecture: CPUID:
Process node: 14nm
Microarchitecture: CPUID:
Process node: 14nm
nameCore i3/5/7 & Xeon E3 (Kaby Lake) Core i3/5/7 & Xeon E3 v6 (Kaby Lake) -
Chip family#347has been inserted by helencroftAttribute Old value New value idnull 347 miscSpecsnull namenull MCS-85 -
Chip family#42(K6-2 - Model 8 (Chomper/CXT)) has been associated toEntity documentation#217(Embedded AMD-K6 Processors BIOS Design Guide (23913A) [2000-11]) by computerguy096 -
Chip family#42(K6-2 - Model 8 (Chomper/CXT)) has been associated toEntity documentation#216(AMD-K6 Processor BIOS Design (21329) [1999-12]) by computerguy096 -
Chip family#42has been updated by computerguy096Attribute Old value New value miscSpecsMicroarchitecture: CPUID: 0: 580 (model 8)<br/>1: 58C (model 8)<br/><br/>L1... Microarchitecture: CPUID: 580 (model 8),58C (model 8)<br/>L1 cache: 32KB co... -
Chip family#76(K6-2+/III+ - Model 13) has been associated toEntity documentation#215(AMD K6-2E+ Embedded Processor Data Sheet (23542, rev.A) [2000-09]) by computerguy096 -
Chip family#76has been updated by computerguy096Attribute Old value New value miscSpecsMicroarchitecture: CPUID: 0: 5D0 (model 13)<br/><br/>L1 cache: 32KB code, 3... Microarchitecture: CPUID: 5D0 (model 13)<br/>L1 cache: 32KB code, 32KB data... -
Chip family#346(UltraSPARC IIe) has been associated toInstruction set#40(SPARC V9) by PancakePuppy -
Chip family#346(UltraSPARC IIe) has been associated toRAM type#26(SDR RDIMM ECC) by PancakePuppy -
Chip family#346(UltraSPARC IIe) has been associated toRAM type#20(SDR UDIMM ECC) by PancakePuppy -
Chip family#346has been inserted by PancakePuppyAttribute Old value New value idnull 346 miscSpecsnull namenull UltraSPARC IIe -
Chip family#345(ThunderX2) has been associated toEntity documentation#214(Energy, Oil & Gas on Marvell ThunderX2 Whitepaper []) by Wolt1x -
Chip family#345(ThunderX2) has been associated toEntity documentation#213(Manufacturing Applications on Marvell ThunderX2 Whitepaper []) by Wolt1x -
Chip family#345(ThunderX2) has been associated toEntity documentation#212(TI TIDA-01367 High-Power Voltage Regulator Reference Design for Cavium ThunderX2 []) by Wolt1x -
Chip family#345(ThunderX2) has been associated toEntity documentation#211(Building high performance Ceph Object Stores with Cavium ThunderX2 Whitepaper []) by Wolt1x -
Chip family#345(ThunderX2) has been associated toEntity documentation#210(Product Brief []) by Wolt1x -
Chip family#345(ThunderX2) has been associated toRAM type#37(DDR4 UDIMM) by Wolt1x -
Chip family#345has been inserted by Wolt1xAttribute Old value New value idnull 345 miscSpecsnull namenull ThunderX2 -
Chip family#344(ThunderX) has been associated toRAM type#37(DDR4 UDIMM) by Wolt1x -
Chip family#344(ThunderX) has been associated toRAM type#13(DDR3 UDIMM) by Wolt1x -
Chip family#344has been inserted by Wolt1xAttribute Old value New value idnull 344 miscSpecsnull namenull ThunderX -
Chip family#5(486 (3.3V)) has been associated toEntity documentation#207(Intel DX4 datasheet (272771-001) [1995-10]) by computerguy096 -
Chip family#5(486 (3.3V)) has been associated toEntity documentation#206(Am5x86 datasheet (publication 19751, rev.C) [1996-03]) by computerguy096 -
Chip family#5(486 (3.3V)) has been associated toEntity documentation#205(Cyrix 5x86 datasheet (94192-00) [1995-07]) by computerguy096 -
Chip family#5has been updated by computerguy096Attribute Old value New value miscSpecsMicroarchitecture: CPUID:
Process node:
Microarchitecture: CPUID:
Process node:
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Chip family#72has been updated by computerguy096Attribute Old value New value miscSpecsMicroarchitecture: CPUID: <br/>L1 cache: 64KB code, 64KB data<br/>Process n... Microarchitecture: CPUID:
L1 cache: 64KB code, 64KB data
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Chip family#107has been updated by computerguy096Attribute Old value New value miscSpecsMicroarchitecture: CPUID:
Process node:
Microarchitecture: CPUID:
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Chip family#104has been updated by computerguy096Attribute Old value New value miscSpecsMicroarchitecture: CPUID:
Process node:
Microarchitecture: CPUID:
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Chip family#114has been updated by computerguy096Attribute Old value New value miscSpecsMicroarchitecture: CPUID:
Process node: 45nm
Microarchitecture: CPUID:
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Chip family#205has been updated by computerguy096Attribute Old value New value miscSpecsMicroarchitecture: CPUID: <br/>L1 cache: 32KB code, 32KB data<br/>Process n... Microarchitecture: CPUID: 1067A<br/>L1 cache: 32KB code, 32KB data<br/><br/... -
Chip family#94has been updated by computerguy096Attribute Old value New value miscSpecsMicroarchitecture: CPUID:
Process node: 45nm
Microarchitecture: CPUID:
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Chip family#47has been updated by computerguy096Attribute Old value New value miscSpecsMicroarchitecture: CPUID: <br/>L1 cache: 32KB code, 32KB data<br/>Process n... Microarchitecture: CPUID:
L1 cache: 32KB code, 32KB data
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Chip family#343has been inserted by Wolt1xAttribute Old value New value idnull 343 miscSpecsnull namenull K15 - Trinity/Richland -
Chip family#223has been updated by Wolt1xAttribute Old value New value miscSpecsMicroarchitecture: CPUID:
Process node: 28nm
Microarchitecture: CPUID:
Process node: 28nm
nameK15 - Kaveri K15 - Kaveri/Godavari -
Chip family#340(MCS-51) has been associated toEntity documentation#203(MCS-51 Microcontroller Family User's Manual [1994-02]) by helencroft -
Chip family#341(MCS-48) has been associated toEntity documentation#202(MCS-48 Microcomputer User's Manual [1978]) by helencroft -
Chip family#342has been inserted by helencroftAttribute Old value New value idnull 342 miscSpecsnull namenull i960 -
Chip family#341has been inserted by helencroftAttribute Old value New value idnull 341 miscSpecsnull namenull MCS-48
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