
//-------- DO NOT EDIT THIS FILE --------
//
// FILE WAS GENERATED AUTOMATICALY USING AMISDL v3.64.1065 Test Only (Mar 15 2013,03:42:45)
//
//-------- DO NOT EDIT THIS FILE --------
//****************************************************************************
//****************************************************************************
//**                                                                        **
//**         (C)Copyright 1985-2013, American Megatrends, Inc.              **
//**                                                                        **
//**                          All Rights Reserved.                          **
//**                                                                        **
//**         5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
//**                                                                        **
//**                          Phone (770)-246-8600                          **
//**                                                                        **
//****************************************************************************
//****************************************************************************
//****************************************************************************
#if !defined(_TOKEN_SDL_H)
#define _TOKEN_SDL_H
#define CORE_MAJOR_VERSION	0x4
#define CORE_MINOR_VERSION	0x6
#define CORE_REVISION	0x5
#define CORE_BUILD_NUMBER	0x5
#define CORE_COMBINED_VERSION	0x4028f
#define CORE_VENDOR	American Megatrends
#define EMBEDDED_RESOURCES	0
#define ISA_IRQ_MASK	0xe305
#define ISA_DMA_MASK	0x10
#define KBC_SUPPORT	1
#define NV_SIMULATION	0
#define NVRAM_HEADER_SIZE	0x60
#define MANUFACTURING_MODE_SUPPORT	0
#define TRACE_LEVEL_MASK	TRACE_ALWAYS
#define UART_INPUT_CLOCK	0x1c2000
#define SETUP_DATA_LAYOUT_OVERRIDE_SUPPORT	0
#define FORCE_SETUP_ON_FAILED_RECOVERY	1
#define EXTERNAL_DMA_CAPABLE_DEVICES_SUPPORT	0
#define PS2Ctl_SUPPORT	1
#define GC_COLOR_BLACK	0,0,0
#define GC_COLOR_BLUE	0x98,0,0
#define GC_COLOR_GREEN	0,0x98,0
#define GC_COLOR_CYAN	0x98,0x98,0
#define GC_COLOR_RED	0,0,0x98
#define GC_COLOR_MAGENTA	0x98,0,0x98
#define GC_COLOR_BROWN	0x0,0x40,0x80
#define GC_COLOR_LIGHTGRAY	0x98,0x98,0x98
#define GC_COLOR_DARKGRAY	0x10,0x10,0x10
#define GC_COLOR_LIGHTBLUE	0xFF,0x10,0x10
#define GC_COLOR_LIGHTGREEN	0x10,0xFF,0x10
#define GC_COLOR_LIGHTCYAN	0xFF,0xFF,0xE0
#define GC_COLOR_LIGHTRED	0x10,0x10,0xFF 
#define GC_COLOR_LIGHTMAGENTA	0xF0,0x10,0xFF
#define GC_COLOR_YELLOW	0x10,0xFF,0xFF
#define GC_COLOR_WHITE	0xFF,0xFF,0xFF
#define GC_MODE1	{ 1, 80, 50, 1280, 1024 }
#define GC_MODE2	{ 2, 100, 31, 800, 600 }
#define GC_MODE3	{ 3, 0, 0, 0, 0 }
#define GC_MODE_LIST	{ 0, 80, 25, 0, 0 }, { 1, 80, 50, 1280, 1024 }, { 2, 100, 31, 800, 600 }, { 3, 0, 0, 0, 0 }
#define PS2MOUSE_SUPPORT	1
#define PS2KBD_SUPPORT	1
#define BLOCK_KBC_PIN_22_23_BIT	1
#define LEDS_AT_STARTUP	0x2
#define MAX_HOTKEYS	0x14
#define INIT_DEFAULT_HOTKEYS	1
#define KBC_BASIC_ASSURANCE_TEST	1
#define KB_IRQ_SUPPORT	0
#define MS_IRQ_SUPPORT	0
#define IBFREE_TIMEOUT	0x12c
#define CLEAR_PS2KB_BUFFER_AT_READYTOBOOT	0
#define CHECK_BDA_KEYBOARD_BUFFER	1
#define CLEAR_PENDING_KEYS_IN_PS2	0
#define BBS_USB_DEVICE_TYPE_SUPPORT	0
#define BBS_NETWORK_DEVICE_TYPE_SUPPORT	0
#define GROUP_BOOT_OPTIONS_BY_TAG	1
#define FW_ORPHAN_BOOT_OPTIONS_POLICY	ORPHAN_BOOT_OPTIONS_POLICY_DELETE
#define NON_FW_ORPHAN_BOOT_OPTIONS_POLICY	ORPHAN_BOOT_OPTIONS_POLICY_HIDE
#define ORPHAN_GROUP_HEADERS_POLICY	ORPHAN_BOOT_OPTIONS_POLICY_DELETE
#define BOOT_OPTION_NAME_PREFIX_FUNCTION	ConstructBootOptionNamePrefixDefault
#define BOOT_OPTION_NAME_SUFFIX_FUNCTION	ConstructBootOptionNameSuffixDefault
#define BOOT_OPTION_GET_BBS_ENTRY_DEVICE_TYPE_FUNCTION	GetBbsEntryDeviceTypeDefault
#define MATCH_BOOT_OPTION_BY_DEVICE	1
#define ATAPI_BUSY_CLEAR_TIMEOUT	0x3e80
#define DMA_ATA_COMMAND_COMPLETE_TIMEOUT	0x1388
#define DMA_ATAPI_COMMAND_COMPLETE_TIMEOUT	0x3e80
#define ATAPI_RESET_COMMAND_TIMEOUT	0x1388
#define RESET_RUNTIME_SERVICES_SUPPORT	1
#define NVRAM_MONOTONIC_COUNTER_SUPPORT	1
#define NVRAM_RECORD_CHECKSUM_SUPPORT	0
#define MASTER_SLAVE_ENUMERATION	1
#define IDEBUSMASTER_SUPPORT	1
#define ATAPI_BUSMASTER_SUPPORT	1
#define ACOUSTIC_MANAGEMENT_SUPPORT	0
#define IDE_POWER_MANAGEMENT_SUPPORT	0
#define ADVANCED_POWER_MANAGEMENT_LEVEL	0x1
#define POWERUP_IN_STANDBY_MODE	0
#define HOST_PROTECTED_AREA_SUPPORT	0
#define IDE_HP_SUPPORT	0
#define EFI_IDE_PROTOCOL	1
#define INTEL_IDE_PROTOCOL	1
#define AHCI_COMPATIBLE_MODE	0
#define Recovery_SUPPORT	1
#define RECOVERY_DEVICE_ORDER	CAPSULE, BLOCK, SERIAL
#define FAT_RECOVERY_SUPPORT	1
#define SEARCH_FAT_PATH	0
#define NTFS_RECOVERY_SUPPORT	1
#define EXT_RECOVERY_SUPPORT	1
#define CD_RECOVERY_SUPPORT	1
#define ATAPI_RECOVERY_SUPPORT	1
#define SERIAL_RECOVERY_SUPPORT	1
#define ATA_RECOVERY_SUPPORT	1
#define NTFS_NAME_CORRECTION	1
#define RECOVERY_SCAN_RETRIES	0x3
#define RECOVERY_ROM	flashabl.ROM
#define RECOVERY_IMAGE_SIZE	0x800000
#define REFLASH_INTERACTIVE	1
#define REFLASH_UPDATE_NVRAM_CONTROL	1
#define REFLASH_UPDATE_NVRAM	1
#define REFLASH_UPDATE_BOOT_BLOCK_CONTROL	0
#define REFLASH_UPDATE_MAIN_BLOCK	1
#define PCI_BUS_MAJOR_VER	0x2
#define PCI_BUS_MINOR_VER	0x5
#define PCI_BUS_REVISION	0x2
#define PCI_BUS_VER_COMBINED	0xfc
#define HOTPLUG_SUPPORT	0
#define PCI_EXPRESS_SUPPORT	1
#define PCI_X_SUPPORT	0
#define PCI_FIXED_BUS_ASSIGNMENT	0
#define PCI_DEV_REVERSE_SCAN_ORDER	0
#define PCI_SCAN_FULL_BUS_RANGE	0
#define PCI_4K_RESOURCE_ALIGNMENT	1
#define SRIOV_SUPPORT	0
#define PCI_DEVICE_IO_RESOURCE_THRESHOLD	0xffff
#define PCI_DEVICE_32BIT_RESOURCE_THRESHOLD	0xffffffff
#define COMBINE_MEM_PMEM	0
#define PCI_MMIO_RES_TOP_ALLIGN	0
#define PCI_AMI_COMBINE_MEM_PMEM32	0
#define PCI_T_RST	0x3e8
#define PCI_T_RST_RECOVERY	0x186a0
#define AmiBoardInfo_SUPPORT	1
#define AMI_BOARD_INFO_MAJOR_VERSION	0x2
#define AMI_BOARD_INFO_MINOR_VERSION	0x1
#define AMI_BOARD_VER_COMBINED	0xd2
#define PlatformToDriver_SUPPORT	1
#define MAX_PEI_PERF_LOG_ENTRIES	0x1c
#define MINIMUM_YEAR	0x7ce
#define FAT_CACHE_SIZE	0x4000
#define DXE_STACK_SIZE	0x100000
#define CURSOR_BLINK_ENABLE	0
#define OemGetExtFont	AmiGetExtFont
#define REPORT_NO_CON_OUT_ERROR	1
#define REPORT_NO_CON_IN_ERROR	1
#define FirmwareManagementr_SUPPORT	1
#define HashService_SUPPORT	1
#define PCI_BUS_SKIP_BRG_RECURSIVELY	0
#define Capsule2_0_SUPPORT	1
#define SUPPORT_UPDATE_CAPSULE_RESET	1
#define MAX_CAPSULE_SIZE	0x4000000
#define LargeFont_SUPPORT	1
#define PUBLISH_CUSTOM_FONTS	0
#define AST2300_SUPPORT	1
#define SIO_SUPPORT	1
#define AST2300_CONFIG_INDEX	0x4e
#define AST2300_CONFIG_DATA	0x4f
#define SIO_SB_BUS_NUM	0x0
#define SIO_SB_FUNC_NUM	0x0
#define AST2300_LDN_UART0	0x2
#define AST2300_LDN_UART1	0x3
#define AST2300_LD_SEL_REGISTER	0x7
#define AST2300_ACTIVATE_REGISTER	0x30
#define AST2300_BASE1_HI_REGISTER	0x60
#define AST2300_BASE1_LO_REGISTER	0x61
#define AST2300_IRQ1_REGISTER	0x70
#define AST2300_ACTIVATE_VALUE	0x1
#define AST2300_DEACTIVATE_VALUE	0x0
#define AST2300_SERIAL_PORT1_BASE_ADDRESS	0x3f8
#define DEBUG_LDN_UART	0x2
#define AST2300_SERIAL_PORT2_BASE_ADDRESS	0x2f8
#define AST2300_SERIAL_PORT1_PRESENT	1
#define AST2300_SERIAL_PORT2_PRESENT	1
#define CORE_AFTER_4634	1
#define CORE_VERSION_VALUE	0x122f
#define PILOT3_SIO_SUPPORT	0
#define IT8728_SUPPORT	0
#define IT8732_SUPPORT	0
#define FLASH_ERASE_POLARITY	0x1
#define FLASH_RETRIES	0x3
#define FLASH_ERASE_TIMEOUT	0x2faf080
#define FLASH_PROGRAM_TIMEOUT	0x2faf080
#define NUMBER_OF_BYTES_PER_PAGE	0x40
#define FLASH_PART_STRING_LENGTH	0x30
#define DIRECT_FLASH_MEMORY_ACCESS	1
#define Spansion_29GLxxx	1
#define Numonyx_256P30x	1
#define Mxic_29LVxxx	1
#define SPIFlash_SUPPORT	1
#define SST_25VFxxx	1
#define SST_25LFxxx	1
#define STM_25PExx	1
#define ATMEL_26DFxxx	1
#define Numonyx_M25P128	0
#define FAST_READ_SUPPORT	0x0
#define AAI_WORD_PROGRAM	0
#define BLOCK_PROTECT_ENABLE	0
#define LOWER_VSCC_REG	0xc4
#define UPPER_VSCC_REG	0xc8
#define BroadwellPkg_SUPPORT	1
#define INTEL_CPURC_SUPPORT	1
#define BIST_SUPPORT	0
#define CpuRatioOverride_Support	0
#define DcaState_token	0
#define FastString_token	1
#define MachineCheckEnable_token	1
#define DcaPrefetchDelayValue_token	4
#define VirtualWireMode_token	0
#define CpuInitDxe_SUPPORT	1
#define REQUEST_EBDA_SIZE	0x1000
#define CpuInitPei_SUPPORT	1
#define Intel_Haswell_SEC_RC_SUPPORT	1
#define Haswell_PowerMgmtDxe_SUPPORT	1
#define Haswell_PowerMgmtS3_SUPPORT	1
#define CpuPeiPolicySupport	1
#define CpuDxePolicy_SUPPORT	1
#define Haswell_DigitalThermalSensorSmm_SUPPORT	1
#define TxtPei_SUPPORT	1
#define TXT_TOOL_DIR	$(TXT_DIR)\Tools
#define AP_GUID	D1E59F50-E8C3-4545-BF61-11F002233C97
#define AP_OFFSET	0x120000
#define TxtDxe_SUPPORT	1
#define AP_FIXUP_FILE	$(TxtTools_DIR)\Apfixup.txt
#define TxtOneTouchSupport	1
#define SmmThunk_SUPPORT	0
#define SmramSaveInfoHandlerSmm_SUPPORT	1
#define BiosGuardServices_SUPPORT	1
#define NUMBER_CPU_SOCKETS	0x1
#define CPU_SETUP_SET_MAX_RATIO	0
#define CPU_SETUP_SET_BOOT_RATIO	0
#define CPU_SETUP_SET_LATENCY_CONTROL	0
#define CPU_DISPLAY_SETUP_SMX	1
#define RC_POLICY_POWER_UNIT	0
#define MTRR_POLICY	0x1
#define CPU_MAX_IO_SIZE	0x10000
#define SW_SMI_PSTATE_CNT	0x0
#define SW_SMI_CST_CNT	0x0
#define LOCAL_APIC_BASE	0xfee00000
#define APIC_ID_REGISTER	0x20
#define APIC_VERSION_REGISTER	0x30
#define APIC_SPURIOUS_VECTOR_REGISTER	0xf0
#define APIC_ICR_LOW_REGISTER	0x300
#define APIC_ICR_HIGH_REGISTER	0x310
#define APIC_LVT_LINT0_REGISTER	0x350
#define APIC_LVT_LINT1_REGISTER	0x360
#define PEI_CACHE_FLASH_ENABLED	1
#define CODE_CACHE_BASE_ADDRESS	0xfff00000
#define WDB_REGION_BASE_ADDRESS	0x0
#define WDB_REGION_BASE_SIZE	0x1000
#define SMM_FROM_SMBASE_DRIVER	0x55
#define SMM_BASE_SAVE_STATE_OFFSET	0xfef8
#define MAX_SMM_SAVE_STATE_SIZE	0x400
#define IED_SAVESTATE_OFFSET	0xfeec
#define ACPI_INFO2_PROTOCOL_PUBLISHED	1
#define I3_CPU_NON_TURBO	1
#define BRAND_STRING_WORKAROUND	0
#define FIVR_SpreadSpectrum_SUPPORT	1
#define FIVR_SpreadSpectrum_Percent	0x3c
#define FIVR_SpreadSpectrumNotch_Percent	0x0
#define MPDTable_CREATED	1
#define CPU_CACHE_L4_DISPLAY_IN_SMBIOS	0
#define SMBIOS_TYPE_4_PROC_FAMILY	0x0
#define SMBIOS_TYPE_4_ASSET_TAG	Fill By OEM
#define SMBIOS_TYPE_4_PART_NUMBER	Fill By OEM
#define SMBIOS_TYPE_4_SOCKET_DESIGINTATION_SOCKET_0	SOCKET 0
#define SMBIOS_TYPE_7_L1_SOCKET_DESIGNATION	CPU Internal L1
#define SMBIOS_TYPE_7_L2_SOCKET_DESIGNATION	CPU Internal L2
#define SMBIOS_TYPE_7_L3_SOCKET_DESIGNATION	CPU Internal L3
#define SW_SMI_SAVE_MSR	0x56
#define SW_SMI_RESTORE_MSR	0x57
#define SW_SMI_S3_RESTORE_MSR_FROM_SDL	0x59
#define AMI_CPU_S3_PEI_SUPPORT	1
#define SB_TEMPLATE_VER	0x6
#define SB_RESET_PPI_SUPPORT	1
#define COLD_RESET_WITH_POWER_CYCLE	0
#define SB_STALL_PPI_SUPPORT	1
#define OEM_UPDATE_VSCC_TABLE_SUPPORT	0
#define PERFORM_KBC_RESET	0
#define HECI_BASE_ADDRESS	0xfedb0000
#define HECI2_BASE_ADDRESS	0xfedc0000
#define SMBUS_BASE_ADDRESS	0x580
#define SMBS	0x580
#define SMBL	0x20
#define SB_PIRQ_ROUTER_VID	0x8086
#define SB_PIRQ_ROUTER_DID	0x27b8
#define SPI_BASE_ADDRESS	0x3800
#define PM_BASE_ADDRESS	0x1800
#define PBLK	0x1810
#define TCO_BASE_ADDRESS	0x1860
#define GPIO_BASE_ADDRESS	0x1c00
#define GPI_IRQ_2_IOXAPIC	0xffff
#define SW_SMI_IO_ADDRESS	0xb2
#define SW_SMI_IO_DATA_ADDRESS	0xb3
#define COUGAR_POINT_SKU	0x0
#define SPI_READ_CONFIG	0x2
#define HIDE_BIOS_SECURITY_PAGE	0
#define SMI_LOCK_ENABLE	1
#define BIOS_INTERFACE_LOCKDOWN	1
#define BIOS_LOCK_IOTRAP_SMI	0x78
#define GPIO_LOCKDOWN_ENABLE	0
#define RC_BLE_SET	0
#define RTC_LOCK_ENABLE	0
#define INIT_RTC_ALWAYS	0
#define DISABLE_DAYLIGHT_SAVINGS	0
#define DEFAULT_CRID_ENABLE	0
#define PCH_PWR_OPT_DMI	1
#define PCH_PWR_OPT_GBE	1
#define PCH_PWR_OPT_XHCI	0
#define PCH_PWR_OPT_EHCI	0
#define PCH_PWR_OPT_SATA	1
#define NUM_OF_DEVLTR_OVERRID	0x0
#define DEVLTR_OVERRID	0
#define LEGACY_DMA_DISABLE	0
#define ULT_USB_PORTS_LENGTH	0x79, 0x78, 0x52, 0x105, 0x92, 0x88, 0x47, 0x43, 0x100, 0x100, 0x100, 0x100, 0x100, 0x100
#define ULT_USB_OVER_CURRENT_MAPPING_SETTINGS	0, 0, 8, 8, 2, 2, 1, 1
#define ULT_USB30_OVER_CURRENT_MAPPING_SETTINGS	0, 0, 8, 8
#define ULT_USB_PORT_LOCATION_CONFIG	0, 0, 3, 2, 0, 0, 1, 1, 6, 6, 6, 6, 6, 6
#define EHCI_CON_DISCON_WAKE_UP_SUPPORT	0
#define OEM_USB_PER_PORT_DISABLE_SUPPORT	0
#define XHCI_MANUAL_MODE_SUPPORT	0
#define USB_ENDPOINT_SUPPORT	0
#define AMI_USB_XHCI_THERMAL_THROTTLING	0
#define AMI_USB30_FIXED_EQUALIZATION_PORT0	0
#define AMI_USB30_FIXED_EQUALIZATION_PORT1	0
#define AMI_USB30_FIXED_EQUALIZATION_PORT2	0
#define AMI_USB30_FIXED_EQUALIZATION_PORT3	0
#define AMI_USB30_FIXED_EQUALIZATION_PORT4	0
#define AMI_USB30_FIXED_EQUALIZATION_PORT5	0
#define USB30_IOBP_PORT0	0, 0, 0, 0, 0, FALSE, FALSE, FALSE, FALSE, 0
#define USB30_IOBP_PORT1	0, 0, 0, 0, 0, FALSE, FALSE, FALSE, FALSE, 0
#define USB30_IOBP_PORT2	0, 0, 0, 0, 0, FALSE, FALSE, FALSE, FALSE, 0
#define USB30_IOBP_PORT3	0, 0, 0, 0, 0, FALSE, FALSE, FALSE, FALSE, 0
#define USB30_IOBP_PORT4	0, 0, 0, 0, 0, FALSE, FALSE, FALSE, FALSE, 0
#define USB30_IOBP_PORT5	0, 0, 0, 0, 0, FALSE, FALSE, FALSE, FALSE, 0
#define SB_PCI_DEVICES_SSID_TABLE	{SIO_DMA_BUS_DEV_FUN, -1}, {SIO_I2C0_BUS_DEV_FUN, -1}, {SIO_I2C1_BUS_DEV_FUN, -1}, {SIO_GSPI0_BUS_DEV_FUN, -1}, {SIO_GSPI1_BUS_DEV_FUN, -1}, {SIO_UART0_BUS_DEV_FUN, -1}, {SIO_UART1_BUS_DEV_FUN, -1}, {SIO_SDIO_BUS_DEV_FUN, -1}, {HECI_BUS_DEV_FUN, -1}, {HECI_BUS_DEV_FUN, -1}, {HECI2_BUS_DEV_FUN, -1}, {IDER_BUS_DEV_FUN, -1}, {KT_BUS_DEV_FUN, -1}, {LAN_BUS_DEV_FUN, -1}, {XHCI_BUS_DEV_FUN, -1}, {EHCI2_BUS_DEV_FUN, -1}, {HDA_BUS_DEV_FUN, -1}, {PCIEBRS_BUS_DEV_FUN, -1}, {PCIEBRS2_BUS_DEV_FUN, -1}, {PCIEBRS3_BUS_DEV_FUN, -1}, {PCIEBRS4_BUS_DEV_FUN, -1}, {PCIEBRS5_BUS_DEV_FUN, -1}, {PCIEBRS6_BUS_DEV_FUN, -1}, {PCIEBRS7_BUS_DEV_FUN, -1}, {PCIEBRS8_BUS_DEV_FUN, -1}, {EHCI_BUS_DEV_FUN, -1}, {PCIBR_BUS_DEV_FUN, -1}, {SB_BUS_DEV_FUN, -1}, {SATA_BUS_DEV_FUN, -1}, {SMBUS_BUS_DEV_FUN, -1}, {SATA2_BUS_DEV_FUN, -1}, {THERMAL_BUS_DEV_FUN, -1}, {-1, -1}
#define TSGPIO_C_PMSYN	1
#define TSGPIO_D_PMSYN	1
#define TSGPIO_C_C0_TRANSMIT	1
#define TSGPIO_D_C0_TRANSMIT	1
#define TSGPIO_C_PIN_SEL	0x1
#define TSGPIO_D_PIN_SEL	0x0
#define DEVICE_NAME_LENGTH	0xe
#define SB_SWSMI_WRITE_TO_BOOTSCRIPT	1
#define PCH_IO_APIC_ID	0x8
#define PCH_APIC_RANGE_SELECT	0x0
#define HDA_RESET_WAIT_TIMER	0x12c
#define ME_WAKE_STS	1
#define ME_HRST_COLD_STS	1
#define ME_HRST_WARM_STS	1
#define PCH_SLP_S3_MIN_ASSERT_VALUE	0x2
#define PCH_SLP_SUS_MIN_ASSERT_VALUE	0x3
#define PCH_SLPA_MIN_ASSERT_VALUE	0x3
#define SLP_STRCH_SUS_UP	0
#define TTLEVELS_SUGGEST	1
#define DMIHAAWC_SUGGEST	1
#define SATATT_SUGGEST	1
#define SIRQ_ENABLE	1
#define SIRQ_START_FRAME_PULSE	0x0
#define PCH_PCIE_PME_INTERRUPT	0
#define PCH_PCIE_COMPLETION_TIME_OUT	0x0
#define AMI_PCIE_THROTTLING_PORT0	0
#define AMI_PCIE_THROTTLING_PORT1	0
#define AMI_PCIE_THROTTLING_PORT2	0
#define AMI_PCIE_THROTTLING_PORT3	0
#define AMI_PCIE_THROTTLING_PORT4	0
#define AMI_PCIE_THROTTLING_PORT5	0
#define AMI_PCIE_THROTTLING_PORT6	0
#define AMI_PCIE_THROTTLING_PORT7	0
#define PCH_PCIE_TEMP_RP_BUS_NUM_MIN	0x2
#define PCH_PCIE_TEMP_RP_BUS_NUM_MAX	0x4
#define MAX_EXTRA_BUS_RESERVED	0x7
#define MAX_PCIE_MEM_RESERVED	0x14
#define MAX_PCIE_PF_MEM_RESERVED	0x14
#define MAX_PCIE_IO_RESERVED	0x14
#define SB_PCIE_PFMEM_ABOVE_4G	0
#define SATA_MODE_IDE	0x0
#define SATA_MODE_AHCI	0x1
#define SATA_MODE_RAID	0x2
#define FORCE_USER_TO_SETUP_IF_CMOS_BAD	0
#define SYSTEM_REBOOT_NORMALLY_IF_S3_IS_FAILED	0
#define HOST_WLAN_PP_EN	0
#define ONLY_CLEAR_RTC_EN_IN_PEI	1
#define SB_CMOS_MISC_FLAG_REG	0x90
#define SB_GEN_DECODE_RANGE_1	0x0
#define SB_GEN_DECODE_RANGE_2	0x0
#define SB_GEN_DECODE_RANGE_3	0x0
#define SB_GEN_DECODE_RANGE_4	0x0
#define PROGRAM_DEFAULT_GPIO	1
#define PROGRAM_GPIO_TYPE	0
#define IS_GPIO	0x1
#define IS_NOT_GPIO	0x0
#define IS_GPI	0x2
#define IS_GPO	0x0
#define OUTPUT_HIGH	0x4
#define OUTPUT_LOW	0x0
#define GPO_HIGH	0x5
#define GPO_LOW	0x1
#define GPI_NON_INV	0x0
#define GPI_INV	0x8
#define GPO_BLINK	0x10
#define GPIO_RESET	0x20
#define GPIO_OWN_ACPI	0x0
#define GPIO_OWN_GPIO	0x40
#define GPI_LEB_EDGE	0x0
#define GPI_LEB_LEVEL	0x80
#define GPI_NDIS_ENABLE	0x0
#define GPI_NDIS_DISABLE	0x100
#define GPIO_GPIWP_NONE	0x0
#define GPIO_GPIWP_DOWN	0x200
#define GPIO_GPIWP_UP	0x400
#define GPIO_GPIWP_INVALID	0x600
#define GPI_INT_ENABLE	0x800
#define APCB	0xfec00000
#define APCL	0x1000
#define SW_SMI_SB_ACPI_S3	0xb8
#define ACPI_SCI_INT	0x9
#define PM_SCI_ENABLE	0x1
#define ACPI_ALARM_DAY_CMOS	0xd
#define ACPI_ALARM_MONTH_CMOS	0x0
#define ACPI_CENTURY_CMOS	0x32
#define ACPI_RESET_REG_ADDRESS	0xcf9
#define ACPI_RESET_REG_TYPE	0x1
#define ACPI_RESET_REG_BITWIDTH	0x8
#define ACPI_RESET_REG_BITOFFSET	0x0
#define ACPI_RESET_REG_VALUE	0x6
#define PM1A_EVT_BLK_ADDRESS	0x1800
#define PM1A_EVT_BLK_TYPE	0x1
#define PM1A_EVT_BLK_BITWIDTH	0x20
#define PM1A_EVT_BLK_BITOFFSET	0x0
#define PM1_EVT_LENGTH	0x4
#define PM1A_CNT_BLK_ADDRESS	0x1804
#define PM1A_CNT_BLK_TYPE	0x1
#define PM1A_CNT_BLK_BITWIDTH	0x10
#define PM1A_CNT_BLK_BITOFFSET	0x0
#define PM1_CNT_LENGTH	0x2
#define PM1B_EVT_BLK_ADDRESS	0x0
#define PM1B_EVT_BLK_TYPE	0x1
#define PM1B_EVT_BLK_BITWIDTH	0x0
#define PM1B_EVT_BLK_BITOFFSET	0x0
#define PM1B_CNT_BLK_ADDRESS	0x0
#define PM1B_CNT_BLK_TYPE	0x1
#define PM1B_CNT_BLK_BITWIDTH	0x0
#define PM1B_CNT_BLK_BITOFFSET	0x0
#define PM2_CNT_BLK_ADDRESS	0x1850
#define PM2_CNT_BLK_TYPE	0x1
#define PM2_CNT_BLK_BITWIDTH	0x8
#define PM2_CNT_BLK_BITOFFSET	0x0
#define PM2_CNT_LENGTH	0x1
#define PM_TMR_BLK_ADDRESS	0x1808
#define PM_TMR_BLK_TYPE	0x1
#define PM_TMR_BLK_BITWIDTH	0x20
#define PM_TMR_BLK_BITOFFSET	0x0
#define PM_TMR_LENGTH	0x4
#define GPE0_BLK_ADDRESS	0x1820
#define GPE0_BLK_TYPE	0x1
#define GPE0_BLK_BITWIDTH	0x80
#define GPE0_BLK_BITOFFSET	0x0
#define GPE0_BLK_LENGTH	0x10
#define GPE1_BLK_ADDRESS	0x0
#define GPE1_BLK_TYPE	0x1
#define GPE1_BLK_BITWIDTH	0x0
#define GPE1_BLK_BITOFFSET	0x0
#define GPE1_BLK_LENGTH	0x0
#define GPE1_BASE_OFFSET	0x0
#define PRIMARY_CHANNEL_ENABLE	1
#define PRIMARY_MASTER_DRIVE_ENABLE	1
#define MAX_UDMA	0x5
#define MAX_PIO	0x4
#define PRIMARY_SLAVE_DRIVE_ENABLE	1
#define SECONDARY_CHANNEL_ENABLE	1
#define SECONDARY_MASTER_DRIVE_ENABLE	1
#define SECONDARY_SLAVE_DRIVE_ENABLE	1
#define BUSMASTER_ENABLE	1
#define MASTER_INTERRUPT_BASE	0x58
#define SLAVE_INTERRUPT_BASE	0x70
#define SLEEP_BUTTON_SUPPORT	0
#define HPET_SUPPORT	1
#define HPET_BASE_ADDRESS	0xfed00000
#define HPTB	0xfed00000
#define HPET_PROTOCOL_SUPPORT	0
#define HDD_POWER_LOSS_IN_S3	1
#define CMOS_ADDR_PORT	0x70
#define CMOS_DATA_PORT	0x71
#define CMOS_BAD_REG	0xe
#define DEFAULT_MONTH	0x1
#define DEFAULT_DAY	0x1
#define EARLIEST_YEAR	0x7ce
#define PCI_DEBUG_PORT	0x80
#define SB_TEMP_IO_BASE	0x1200
#define SB_TEMP_IO_BASE_LENGTH	0x10
#define AMI_INIT_VERB_TABLE_IN_S3	0
#define RESERVED_ROM_LENGTH	0x1000000
#define RESERVED_ROM_BASE	0xff000000
#define SB_TEMP_MMIO_BASE	0xfeff0000
#define SB_TEMP_MMIO_BASE_LENGTH	0x10000
#define MAX_NUM_HD_CODECS	0x4
#define KBC_AUTODETECT_PORTS	0
#define SIO_SB_DEV_NUM	0x1f
#define SB_RCRB_BASE_ADDRESS	0xfed1c000
#define SB_RCBA	0xfed1c000
#define SB_RCRB_LENGTH	0x4000
#define RC_PORT_0	1
#define RC_PORT_1	1
#define RC_PORT_2	1
#define RC_PORT_3	1
#define RC_PORT_4	1
#define RC_PORT_5	1
#define RC_PORT_6	1
#define RC_PORT_7	1
#define SX_NOTIFY_PWRB	1
#define PCIE_CLEAR_RETRAIN_BIT_SUPPORT	0
#define EHCI_MMIO_BASE_ADDRESS1	0xfecd0000
#define EHCI_MMIO_BASE_ADDRESS2	0xfecd0c00
#define CLOCK_GENERATOR_SETTINGS	{0x35, 0x83, 0xFF, 0xFF, 0xFC, 0x00, 0x00, 0x26, 0x03, 0x25, 0xFD, 0x56, 0x0D}
#define OFFSET_0	0x0
#define OFFSET_1	0x1
#define OFFSET_2	0x2
#define OFFSET_3	0x3
#define OFFSET_4	0x4
#define OFFSET_5	0x5
#define OFFSET_6	0x6
#define OFFSET_7	0x7
#define OFFSET_8	0x8
#define OFFSET_9	0x9
#define OFFSET_10	0xa
#define OFFSET_11	0xb
#define OFFSET_12	0xc
#define OFFSET_13	0xd
#define SATA_LEGACYMODE	0
#define ESATA_SPEED_LIMIT	0
#define PCIE_NAND_REMAP_DEVICE_RESET_DELAY	0x64
#define PCH_DCI_ENABLE	0
#define PCH_DMIIOT	0
#define PCH_PME_B0_S5_DISABLE	0
#define PCH_WAKE_ON_WLAN_ENABLE	0
#define PCH_WAKE_ON_WLAN_DEEP_SX_ENABLE	0
#define DDR50_SUPPORT	0
#define TSEL_LOCK	1
#define TSC_LOCK	1
#define TSMIC_LOCK	1
#define PHLC_LOCK	1
#define IOAPIC_ENTRY_24_39	1
#define MOD_PHY_COUPLING_ENABLE	1
#define MOD_PHY_PGD_SUPPORT	1
#define PCH_RESET_CYCLE_DURATION	0x4
#define PCH_PCIE_CLOCK_CFG	0
#define ALLOW_NO_LTR_ICC_PLL_SHUTDOWN	0
#define SATA_THROTTLING	1
#define PCH_FLASH_START_ADDRESS	0xff800000
#define SPI_PROTECTED_RANGE_0	{2, FALSE, FALSE, 0x6e0000, 0x120000}
#define SPI_FV_BB_PROTECTED_RANGE_BASE	0x6e0000
#define SPI_FV_BB_PROTECTED_RANGE_LENGTH	0x120000
#define SPI_PROTECTED_RANGE_1	{2, FALSE, FALSE, 0x50000, 0x670000}
#define SPI_FV_MAIN_PROTECTED_RANGE_BASE	0x50000
#define SPI_FV_MAIN_PROTECTED_RANGE_LENGTH	0x670000
#define SPI_PROTECTED_RANGE_2	{2, FALSE, FALSE, 0x6c0000, 0x20000}
#define SPI_FV_DATA_PROTECTED_RANGE_BASE	0x6c0000
#define SPI_FV_DATA_PROTECTED_RANGE_LENGTH	0x20000
#define SPI_PROTECTED_RANGE_3	{0, FALSE, FALSE, 0, 0}
#define SPI_PROTECTED_RANGE_4	{0, FALSE, FALSE, 0, 0}
#define AMI_INTERRUPT_PIN_CONFIG_DEV31_H	PCH_DEV_IP_SETTING(2, INT_B) | PCH_DEV_IP_SETTING(3, INT_C) | PCH_DEV_IP_SETTING(5, INT_B) | PCH_DEV_IP_SETTING(6, INT_C)
#define AMI_INTERRUPT_PIN_CONFIG_DEV29_H	PCH_DEV_IP_SETTING(0, INT_A)
#define AMI_INTERRUPT_PIN_CONFIG_DEV28_H	PCH_DEV_IP_SETTING(0, INT_A) | PCH_DEV_IP_SETTING(1, INT_B) | PCH_DEV_IP_SETTING(2, INT_C) | PCH_DEV_IP_SETTING(3, INT_D) | PCH_DEV_IP_SETTING(4, INT_A) | PCH_DEV_IP_SETTING(5, INT_B) | PCH_DEV_IP_SETTING(6, INT_C) | PCH_DEV_IP_SETTING(7, INT_D)
#define AMI_INTERRUPT_PIN_CONFIG_DEV27_H	PCH_DEV_IP_SETTING(0, INT_A)
#define AMI_INTERRUPT_PIN_CONFIG_DEV26_H	PCH_DEV_IP_SETTING(0, INT_A)
#define AMI_INTERRUPT_PIN_CONFIG_DEV25_H	PCH_DEV_IP_SETTING(0, INT_A)
#define AMI_INTERRUPT_PIN_CONFIG_DEV20_H	PCH_DEV_IP_SETTING(0, INT_A)
#define AMI_INTERRUPT_ROUTE_CONFIG_DEV31_H	PCH_DEV_IR_SETTING( PIRQ_F, PIRQ_D, PIRQ_C, PIRQ_A )
#define AMI_INTERRUPT_ROUTE_CONFIG_DEV28_H	PCH_DEV_IR_SETTING( PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D )
#define AMI_INTERRUPT_ROUTE_CONFIG_DEV27_H	PCH_DEV_IR_SETTING( PIRQ_G, PIRQ_B, PIRQ_C, PIRQ_D )
#define AMI_INTERRUPT_ROUTE_CONFIG_DEV26_H	PCH_DEV_IR_SETTING( PIRQ_A, PIRQ_F, PIRQ_C, PIRQ_D )
#define AMI_INTERRUPT_ROUTE_CONFIG_DEV25_H	PCH_DEV_IR_SETTING(PIRQ_E, PIRQ_F, PIRQ_G, PIRQ_H )
#define AMI_INTERRUPT_ROUTE_CONFIG_DEV20_H	PCH_DEV_IR_SETTING( PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D )
#define AMI_INTERRUPT_PIN_CONFIG_DEV31_LP	PCH_DEV_IP_SETTING(2, INT_B) | PCH_DEV_IP_SETTING(3, INT_C) | PCH_DEV_IP_SETTING(5, INT_B) | PCH_DEV_IP_SETTING(6, INT_C)
#define AMI_INTERRUPT_PIN_CONFIG_DEV29_LP	PCH_DEV_IP_SETTING(0, INT_A)
#define AMI_INTERRUPT_PIN_CONFIG_DEV28_LP	PCH_DEV_IP_SETTING(0, INT_A) | PCH_DEV_IP_SETTING(1, INT_B) | PCH_DEV_IP_SETTING(2, INT_C) | PCH_DEV_IP_SETTING(3, INT_D) | PCH_DEV_IP_SETTING(4, INT_A) | PCH_DEV_IP_SETTING(5, INT_B) | PCH_DEV_IP_SETTING(6, INT_C) | PCH_DEV_IP_SETTING(7, INT_D)
#define AMI_INTERRUPT_PIN_CONFIG_DEV27_LP	PCH_DEV_IP_SETTING(0, INT_A)
#define AMI_INTERRUPT_PIN_CONFIG_DEV25_LP	PCH_DEV_IP_SETTING(0, INT_A)
#define AMI_INTERRUPT_PIN_CONFIG_DEV20_LP	PCH_DEV_IP_SETTING(0, INT_A)
#define AMI_INTERRUPT_ROUTE_CONFIG_DEV31_LP	PCH_DEV_IR_SETTING( PIRQ_F, PIRQ_D, PIRQ_C, PIRQ_A )
#define AMI_INTERRUPT_ROUTE_CONFIG_DEV29_LP	PCH_DEV_IR_SETTING( PIRQ_H, PIRQ_D, PIRQ_A, PIRQ_C )
#define AMI_INTERRUPT_ROUTE_CONFIG_DEV28_LP	PCH_DEV_IR_SETTING( PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D )
#define AMI_INTERRUPT_ROUTE_CONFIG_DEV27_LP	PCH_DEV_IR_SETTING( PIRQ_G, PIRQ_B, PIRQ_C, PIRQ_D )
#define AMI_INTERRUPT_ROUTE_CONFIG_DEV26_LP	PCH_DEV_IR_SETTING( PIRQ_A, PIRQ_F, PIRQ_C, PIRQ_D )
#define AMI_INTERRUPT_ROUTE_CONFIG_DEV25_LP	PCH_DEV_IR_SETTING(PIRQ_E, PIRQ_F, PIRQ_G, PIRQ_H )
#define AMI_INTERRUPT_ROUTE_CONFIG_DEV23_LP	PCH_DEV_IR_SETTING( PIRQ_G,    0x0,   0x0,   0x0 )
#define AMI_INTERRUPT_ROUTE_CONFIG_DEV21_LP	PCH_DEV_IR_SETTING( PIRQ_E, PIRQ_E, PIRQ_F, PIRQ_F )
#define AMI_INTERRUPT_ROUTE_CONFIG_DEV20_LP	PCH_DEV_IR_SETTING( PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D )
#define AMI_INTERRUPT_ROUTE_CONFIG_DEV19_LP	PCH_DEV_IR_SETTING( PIRQ_H,    0x0,    0x0,   0x0 )
#define SATA_IOBP_PORT_0	0, 0, 0, 0, FALSE, FALSE, FALSE, FALSE, 0
#define SATA_IOBP_PORT_1	0, 0, 0, 0, FALSE, FALSE, FALSE, FALSE, 0
#define SATA_IOBP_PORT_2	0, 0, 0, 0, FALSE, FALSE, FALSE, FALSE, 0
#define SATA_IOBP_PORT_3	0, 0, 0, 0, FALSE, FALSE, FALSE, FALSE, 0
#define SATA_IOBP_PORT_4	0, 0, 0, 0, FALSE, FALSE, FALSE, FALSE, 0
#define SATA_IOBP_PORT_5	0, 0, 0, 0, FALSE, FALSE, FALSE, FALSE, 0
#define SB_SETUP_SUPPORT	1
#define SMBUS_BLINDING_PROTOCOL_SUPPORT	1
#define PCH_SPD_WRITE_DISABLE	0x1
#define EXTENDED_SMI	0xf0
#define MAX_SW_SMI_INPUT_VALUE	0xef
#define SUPPORTED_GPIS	0xffff
#define GPI_DISPATCH_BY_BITMAP	0
#define SUPPORTED_TCOS	0x168f
#define MAX_SUPPORTED_IOTRAP_REGS	0x4
#define MAX_SUPPORTED_IOTRAP_LENGTH	0x100
#define ACPI_SLEEP_IN_SMM	1
#define SWSMI_TIMER_INSTEAD	1
#define PI_0_9_CHILD_DISPATCHER_SUPPORT	1
#define BIOS_WRITE_SMI_PATCH_ENABLE	1
#define GPI_DISPATCH2_BY_BITMAP	0
#define SUPPORTED_GPIS2	0xffff
#define SW_SMI_ACPI_ENABLE	0xa0
#define SW_SMI_ACPI_DISABLE	0xa1
#define GPIO_SCI_BITMAP	0x0
#define GPIO_SCI_BITMAP2	0x0
#define ULT_GPIO_SCI_BITMAP	0x0
#define SBSMI_SUPPORT	1
#define SW_SMI_SB_EL_S3	0xb9
#define PchSpiRuntime_GUID	C194C6EA-B68C-4981-B64B-9BD271474B20
#define WdtApp_SUPPORT	1
#define WdtAppDxe_SUPPORT	1
#define WdtAppPei_SUPPORT	1
#define SataDriver_SUPPORT	1
#define PCH_SUPPORT	1
#define CougarPoint_SUPPORT	1
#define PCHLP_SUPPORT	0
#define IntelPchInclude_SUPPORT	1
#define IoTrap_SUPPORT	1
#define PchPciExpressHelpersLib_SUPPORT	1
#define PchSmiDispatcher_SUPPORT	1
#define INTEL_RC_SMI_DISPATCHER_SUPPORT	1
#define FORCE_PWB_PHASE_AS_ENTRY	1
#define SmartTimer_SUPPORT	1
#define WDT_SUPPORT	1
#define WdtDxe_SUPPORT	1
#define WdtPei_SUPPORT	1
#define WDT_SUPPORT_ENABLED	1
#define PEI_MRC_BASE_MEMORY_TEST_ENABLE	0
#define NB_TEMPLATE_VER	0x5
#define NB_NUMBER_OF_HOST_BRG	0x1
#define ROOT_BRIDGE_COUNT	0x1
#define NB_IGFX_FORCE_DISABLE_SUPPORT	0x0
#define RC_PEG_0	1
#define RC_PEG_1	1
#define RC_PEG_2	1
#define NB_SA_PAM_LOCK	0
#define TSEG_SIZE	0x800000
#define IED_SIZE	0x400000
#define PCIEX_LENGTH	0x10000000
#define PCI_REGISTER_MAX	0x1000
#define NCPU	0x8
#define CPU_MAX_MEMORY_SIZE	0x100000000
#define PEI_MIN_MEMORY_SIZE	0x4000000
#define MEMORY_ARRAY_NUM	0x1
#define DIMM1_SMBUS_ADDRESS	0xa0
#define DIMM2_SMBUS_ADDRESS	0xa2
#define DIMM3_SMBUS_ADDRESS	0xa4
#define DIMM4_SMBUS_ADDRESS	0xa6
#define NB_EP_BASE_ADDRESS	0xfed19000
#define NB_DERAM_BASE_ADDRESS	0xfed80000
#define NB_GDXC_BASE_ADDRESS	0xfed84000
#define NB_MCH_BASE_ADDRESS	0xfed10000
#define NB_DMI_BASE_ADDRESS	0xfed18000
#define NB_VTD_BASE_ADDRESS	0xfed90000
#define VTD_LENGTH	0x4000
#define NB_TEMP_MMIO_BASE	0xfd000000
#define NB_TEMP_MMIO_SIZE	0x1000000
#define IGFX_LCD_PANEL_TYPE	0x80
#define IGFX_LCD_PANEL_SCALING	0x81
#define IGFX_BOOT_TYPE	0x82
#define IGFX_BACKLIGHT_TYPE	0x83
#define IGFX_LFP_PANEL_COLOR_DEPTH_TYPE	0x84
#define IGFX_EDP_ACTIVE_LFP_CONFIG_TYPE	0x85
#define IGFX_PRIMARY_DISPLAY_TYPE	0x86
#define IGFX_DISPLAY_PIPE_B_TYPE	0x87
#define IGFX_SDVO_PANEL_TYPE	0x88
#define NB_MRC_CHANNEL_DISABLE_CMOS_ADDR	0x80
#define NB_MRC_EXIT_ON_FAILURE_CMOS_ADDR	0x81
#define OFFSET_14	0xe
#define OFFSET_15	0xf
#define NB_PCI_DEVICES_SSID_TABLE	{NB_BUS_DEV_FUN, -1}, {NB_IGD_BUS_DEV_FUN, -1}, {NB_HDA_BUS_DEV_FUN, -1}, {NB_PCIEBRNx16_BUS_DEV_FUN, -1}, {NB_PCIEBRNx8_BUS_DEV_FUN, -1}, {NB_PCIEBRNx4_BUS_DEV_FUN, -1}, {-1, -1}
#define NB_F0000_PAM0	0x0
#define NB_E0000_PAM5	0x0
#define NB_E8000_PAM6	0x0
#define SG_GPIO_SUPPORT	0
#define NB_SETUP_SUPPORT	1
#define DEFAULT_REFRESH_2X_POLICY	0x0
#define NB_SWSMI_IGFX_GET_SETUP	0xb0
#define DCLK_FREQUENCY	0x0
#define MISC_SUBCLASS_SUPPORT	1
#define SA_EDK_DUMMY_PATCH_SUPPORT	1
#define BoardPciRes_SUPPORT	1
#define PCI_OUT_OF_RESOURCE_SETUP_SUPPORT	1
#define SystemAgent_SUPPORT	1
#define GPIO_dGPU_SELECT	0x34
#define ACTIVE_dGPU_SELECT	0x0
#define SG_DELAY_AFTER_HOLD_RESET	0x64
#define SG_DELAY_AFTER_POWER_ENABLE	0x12c
#define GPIO_dGPU_PRSNT	0x43
#define ACTIVE_dGPU_PRSNT	0x0
#define GPIO_dGPU_PWR_EN	0x36
#define ACTIVE_dGPU_PWR_EN	0x0
#define GPIO_dGPU_PWROK	0x11
#define ACTIVE_dGPU_PWROK	0x1
#define GPIO_dGPU_HOLD_RST	0x32
#define ACTIVE_dGPU_HOLD_RST	0x0
#define GPIO_dGPU_PRSNT_HSW_ULT	0x43
#define ACTIVE_dGPU_PRSNT_HSW_ULT	0x0
#define GPIO_dGPU_PWR_EN_HSW_ULT	0x54
#define ACTIVE_dGPU_PWR_EN_HSW_ULT	0x0
#define GPIO_dGPU_PWROK_HSW_ULT	0x11
#define ACTIVE_dGPU_PWROK_HSW_ULT	0x1
#define GPIO_dGPU_HOLD_RST_HSW_ULT	0x30
#define ACTIVE_dGPU_HOLD_RST_HSW_ULT	0x0
#define GPIO_dGPU_PRSNT_BDW_ULT	0x43
#define ACTIVE_dGPU_PRSNT_BDW_ULT	0x0
#define GPIO_dGPU_PWR_EN_BDW_ULT	0x54
#define ACTIVE_dGPU_PWR_EN_BDW_ULT	0x0
#define GPIO_dGPU_PWROK_BDW_ULT	0x11
#define ACTIVE_dGPU_PWROK_BDW_ULT	0x1
#define GPIO_dGPU_HOLD_RST_BDW_ULT	0x30
#define ACTIVE_dGPU_HOLD_RST_BDW_ULT	0x0
#define GPIO_dGPU_PRSNT_BDW_ULT_VARIANT	0x43
#define ACTIVE_dGPU_PRSNT_BDW_ULT_VARIANT	0x0
#define GPIO_dGPU_PWR_EN_BDW_ULT_VARIANT	0xd
#define ACTIVE_dGPU_PWR_EN_BDW_ULT_VARIANT	0x0
#define GPIO_dGPU_PWROK_BDW_ULT_VARIANT	0x30
#define ACTIVE_dGPU_PWROK_BDW_ULT_VARIANT	0x1
#define GPIO_dGPU_HOLD_RST_BDW_ULT_VARIANT	0x10
#define ACTIVE_dGPU_HOLD_RST_BDW_ULT_VARIANT	0x0
#define SG_ULT_PORT_FUNC	0x4
#define MRC_BDAT_SUPPORT	1
#define MemoryInit_SUPPORT	1
#define CAR_TOTAL_SIZE	0x40000
#define ULT_SUPPORT	0
#define MMA_SUPPORT	0
#define NB_OEM_DIMM1_STATUS	0x1
#define NB_OEM_DIMM2_STATUS	0x1
#define NB_OEM_DIMM3_STATUS	0x1
#define NB_OEM_DIMM4_STATUS	0x1
#define NB_OEM_DIMM1_SPD_DATA	{0x92, 0x10, 0x0B, 0x02, 0x02, 0x11, 0x00, 0x09, 0x03, 0x52, 0x01, 0x08, 0x0A, 0x00, 0xFE, 0x00, 0x69, 0x78, 0x69, 0x30, 0x69, 0x11, 0x18, 0x81, 0x70, 0x03, 0x3C, 0x3C, 0x00, 0xF0, 0x83, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x11, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x98, 0x00, 0x11, 0x11, 0x6B, 0x22, 0x9A, 0x82, 0x11, 0x70}
#define NB_OEM_DIMM2_SPD_DATA	{0x92, 0x10, 0x0B, 0x02, 0x02, 0x11, 0x00, 0x09, 0x03, 0x52, 0x01, 0x08, 0x0A, 0x00, 0xFE, 0x00, 0x69, 0x78, 0x69, 0x30, 0x69, 0x11, 0x18, 0x81, 0x70, 0x03, 0x3C, 0x3C, 0x00, 0xF0, 0x83, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x11, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x98, 0x00, 0x11, 0x11, 0x6B, 0x22, 0x9A, 0x82, 0x11, 0x70}
#define NB_OEM_DIMM3_SPD_DATA	{0x92, 0x10, 0x0B, 0x02, 0x02, 0x11, 0x00, 0x09, 0x03, 0x52, 0x01, 0x08, 0x0A, 0x00, 0xFE, 0x00, 0x69, 0x78, 0x69, 0x30, 0x69, 0x11, 0x18, 0x81, 0x70, 0x03, 0x3C, 0x3C, 0x00, 0xF0, 0x83, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x11, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x98, 0x00, 0x11, 0x11, 0x6B, 0x22, 0x9A, 0x82, 0x11, 0x70}
#define NB_OEM_DIMM4_SPD_DATA	{0x92, 0x10, 0x0B, 0x02, 0x02, 0x11, 0x00, 0x09, 0x03, 0x52, 0x01, 0x08, 0x0A, 0x00, 0xFE, 0x00, 0x69, 0x78, 0x69, 0x30, 0x69, 0x11, 0x18, 0x81, 0x70, 0x03, 0x3C, 0x3C, 0x00, 0xF0, 0x83, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x11, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x98, 0x00, 0x11, 0x11, 0x6B, 0x22, 0x9A, 0x82, 0x11, 0x70}
#define EvLoaderPeim_SUPPORT	0
#define PciHostBridge_SUPPORT	1
#define TOP_LOW_MEM_GRANULARITY	0x10000000
#define SMBIOS_MEMORY_SUPPORT	1
#define SaPcieDxeLib_SUPPORT	1
#define SaPcieSmmLib_SUPPORT	1
#define SA_POLICY_INIT_PEI_SUPPORT	1
#define SaLateInitSmm_SUPPORT	1
#define BdatAccessHandler_SUPPORT	1
#define IntelSaGopDriver_SUPPORT	0
#define IntelSaGopSetup_SUPPORT	0
#define ACPI_MODULE_VER	0x2c
#define ACPI_SUPPORT	1
#define ATAD_SUPPORT	0
#define ACPI_OEM_REV	0x1072009
#define S3_MEMORY_SIZE_PER_CPU	0x1000
#define ACPI_BUILD_TABLES_1_1	0
#define ACPI_BUILD_TABLES_2_0	1
#define ACPI_BUILD_TABLES_3_0	1
#define ACPI_BUILD_TABLES_4_0	1
#define ACPI_BUILD_TABLES_5_0	1
#define FORCE_TO_ACPI1_SETUP_ENABLE	0
#define ACPI_APIC_TBL	1
#define NMIs_QUANTITY	0x0
#define LOCAL_APIC_VERSION_PARAMETER	0x21
#define LAPIC_QUANTITY	0x2
#define LAPIC_0_INT_TYPE	0x3
#define LAPIC_0_POLARITY	0x1
#define LAPIC_0_TRIGGER_MODE	0x1
#define LAPIC_0_SOURCE_BUS_ID	0x0
#define LAPIC_0_SOURCE_BUS_IRQ	0x0
#define LAPIC_0_DEST_ID	0xff
#define LAPIC_0_DEST_LINTIN	0x0
#define LAPIC_1_INT_TYPE	0x1
#define LAPIC_1_POLARITY	0x1
#define LAPIC_1_TRIGGER_MODE	0x1
#define LAPIC_1_SOURCE_BUS_ID	0x0
#define LAPIC_1_SOURCE_BUS_IRQ	0x0
#define LAPIC_1_DEST_ID	0xff
#define LAPIC_1_DEST_LINTIN	0x1
#define IO_APIC_VERSION_PARAMETER	0x21
#define IRQ_00_OVERRIDE_ENABLE	1
#define IRQ_00_APIC_INT	0x2
#define IRQ_00_POLARITY	0x0
#define IRQ_00_TRIGGER_MODE	0x0
#define IRQ_01_OVERRIDE_ENABLE	0
#define IRQ_03_OVERRIDE_ENABLE	0
#define IRQ_04_OVERRIDE_ENABLE	0
#define IRQ_05_OVERRIDE_ENABLE	0
#define IRQ_06_OVERRIDE_ENABLE	0
#define IRQ_07_OVERRIDE_ENABLE	0
#define IRQ_08_OVERRIDE_ENABLE	0
#define IRQ_09_OVERRIDE_ENABLE	1
#define IRQ_09_APIC_INT	0x9
#define IRQ_09_POLARITY	0x1
#define IRQ_09_TRIGGER_MODE	0x3
#define IRQ_10_OVERRIDE_ENABLE	0
#define IRQ_11_OVERRIDE_ENABLE	0
#define IRQ_12_OVERRIDE_ENABLE	0
#define IRQ_13_OVERRIDE_ENABLE	0
#define IRQ_14_OVERRIDE_ENABLE	0
#define IRQ_15_OVERRIDE_ENABLE	0
#define FEC00000_APIC_AUTODETECT	1
#define PCI_BUS_APIC_AUTODETECT	0
#define USE_BOARD_INFO_APIC_DATA	0
#define SW_SMI_S4BIOS	0x0
#define ACPI_RSDT_TABLE_NUM	0x10
#define ACPI_INT_MODEL	0x1
#define ACPI_APIC_FLAGS	0x1
#define P_LVL2_LAT_VAL	0x65
#define P_LVL3_LAT_VAL	0x3e9
#define FLUSH_SIZE_VAL	0x400
#define FLUSH_STRIDE_VAL	0x10
#define FACS_FLAG_S4BIOS	0x0
#define FACS_FLAG_64BIT_WAKE_SUPPORTED	0x0
#define DEFAULT_SS4	0x1
#define DEFAULT_ACPI_LOCK_LEGACY_DEV	0x0
#define DEFAULT_SS3	0x0
#define DEFAULT_SS2	0x0
#define DEFAULT_SS1	0x0
#define DEFAULT_AUTO_ACPI	0x0
#define FACP_FLAG_WBINVD	1
#define FACP_FLAG_WBINVD_FLUSH	0
#define FACP_FLAG_PROC_C1	1
#define FACP_FLAG_P_LVL2_UP	0
#define FACP_FLAG_PWR_BUTTON	0
#define FACP_FLAG_FIX_RTC	0
#define FACP_FLAG_RTC_S4	1
#define FACP_FLAG_TMR_VAL_EXT	0
#define FACP_FLAG_DCK_CAP	0
#define FACP_FLAG_RESET_REG_SUP	1
#define FACP_FLAG_SEALED_CASE	0
#define FACP_FLAG_HEADLESS	0
#define FACP_FLAG_CPU_SW_SLP	0
#define FACP_FLAG_PCI_EXP_WAK	0
#define FACP_FLAG_USE_PLATFORM_CLOCK	0x1
#define FACP_FLAG_S4_RTC_STS_VALID	0x1
#define FACP_FLAG_REMOTE_POWER_ON_CAPABLE	0x1
#define FACP_FLAG_FORCE_APIC_CLUSTER_MODEL	0
#define FACP_FLAG_FORCE_APIC_PHYSICAL_DESTINATION_MODE	0
#define HW_REDUCED_ACPI	0
#define LOW_POWER_S0_IDLE_CAPABLE	0
#define MP_TABLE_LEGACY_REGION_LOCATION	1
#define MP_TBL_TMP_BUFFER_SIZE	0x1000
#define ACPI_THUNK_REAL_MODE_SEGMENT	0x1000
#define ACPI_THUNK_STACK_TOP	0x1000
#define IFDEF_ASL_SUPPORT	1
#define AhciSrc_SUPPORT	1
#define PORT_MULTIPLIER_SUPPORT	0
#define INDEX_DATA_PORT_ACCESS	0
#define HDD_PASSWORD_SUPPORT_UNDER_RAIDMODE	1
#define SUPPORT_ATAPI_IN_RAID_MODE	1
#define DiPM_SUPPORT	1
#define AINT13_SUPPORT	1
#define AHCI_CONTROLLER_COUNT	0x1
#define AI13_BINARY_VERSION	0x1650
#define AHCIMMIOSMM_SUPPORT	0
#define ICH_SATA_BUS_NUMBER	0x0
#define ICH_SATA_DEVICE_NUMBER	0x1f
#define ICH_SATA_FUNCTION_NUMBER	0x2
#define AmiBufferValidationLib_SUPPORT	1
#define OEM_EDID_OVERRIDE_PROTOCOL_SUPPORT	0
#define CMOS_MANAGER_SUPPORT	1
#define CMOS_MANAGER_SOURCE_VERSION	0x28
#define CMOS_RTC_STATUS_REGISTER	0xd
#define CMOS_DIAGNOSTIC_STATUS_REGISTER	0xe
#define CMOS_ACCESS_API_BYTE3	0x42
#define CSMI	0x61
#define CMOS_MANAGER_ASL_SUPPORT	0
#define FULL_CMOS_MANAGER_DEBUG	0
#define FIRST_MANAGED_CMOS_ADDRESS	0x40
#define CMOS_MGR_RECOVER_ONLY_CHECKUMMED	0
#define CMOS_MGR_RECOVER_IN_PEI	1
#define CMOS_SMM_SUPPORT	1
#define CMOS_USES_STANDARD_RANGE_ACCESS	1
#define CMOS_BANK0_INDEX	0x70
#define CMOS_BANK0_DATA	0x71
#define CMOS_MGR_SET_NMI_BIT	1
#define CMOS_NMI_BIT_VALUE	0x80
#define CMOS_SETUP_SUPPORT	0
#define CMOS_MESSAGES_SUPPORT	0
#define CMOS_USES_STANDARD_IS_FIRST_BOOT	1
#define CMOS_USES_STANDARD_IS_BSP	1
#define CMOS_USES_STANDARD_IS_CMOS_USABLE	1
#define CMOS_USES_STANDARD_IS_COLD_BOOT	1
#define CryptoAPI_SUPPORT	1
#define CryptoPPI_SUPPORT	1
#define CR_PEI_MAX_HEAP_SIZE	48*1024
#define CR_DXE_MAX_HEAP_SIZE	48*1024
#define E_CONST	0x01, 0x00, 0x01
#define PSS_SIG_SALTLEN	0x8
#define CONFIG_PEI_PKCS7	0
#define PKCS7_MUTEX_LOCK	0
#define CRYPTO_trace_level	0x0
#define CSM_SUPPORT	1
#define CSM16_VERSION_MAJOR	0x7
#define CSM16_VERSION_MINOR	0x47
#define CSM_VERSION_BUILD	0x50
#define AGGRESSIVELY_JOINED_E820_ENTRIES	0
#define OPROM_MAX_ADDRESS	0xe7fff
#define INT15_D042_SWSMI	0x44
#define CSM_SET_ZIP_EMULATION_TYPE	0
#define FLEXBOOT	0x0
#define CSM_CREATES_ATA_ATAPI_STRINGS	1
#define MAX_ADDITIONAL_P2P_BRIDGES	0x20
#define INT10_VESA_GO_SUPPORT	1
#define INT10_VGA_GO_SUPPORT	0
#define INT10_SIMPLE_TEXT_SUPPORT	1
#define CsmOptOut_SUPPORT	1
#define CSM_OPTOUT_MODULE_REVISION	0x4
#define OLD_OPROM_POLICY_SUPPORT	1
#define DEFAULT_CSM_LAUNCH_POLICY	1
#define DEFAULT_BOOT_OPTION_FILTERING_POLICY	0x0
#define RemoveLegacyGptHddDevice	0
#define RemoveBootOptionWithoutFile	0
#define BootOption_x64	1
#define NORMALIZE_BOOT_OPTION_NAME	0
#define NORMALIZE_BOOT_OPTION_DEVICE_PATH	0
#define G200eGopDriver_SUPPORT	0
#define ErrorLogging_SUPPORT	0
#define SmbiosElogSetupScreen_SUPPORT	0
#define HARDWARE_SIGNATURE_MANAGEMENT_SUPPORT	1
#define HARDWARE_SIGNATURE_USB_CHANGE	0
#define THRESHOLD_OF_DIFFERENT_MEMORY_SIZE	0x80
#define IdeSMART_Support	0
#define INTEL_CHIPSET	1
#define MAX_SHOW_USB_MASS	0x8
#define MAX_DCSCREEN_PAGE	0x3
#define SHOW_IDE_PORT	0
#define SHOW_ATAPI_FULL_INFO	0
#define SHOW_EXTENDED_SATA_PORT	0
#define OEM_DETECT_NO_USB_KB	0x2703
#define OEM_CHASSIS	0x2704
#define OEM_BMCFULL	0x2705
#define OEM_POST_SPERR	0x2708
#define OEM_MEMORY_RESIZE	0x2709
#define ATTRIB_PAUSE	0x3
#define ATTRIB_WARNING	0x2
#define PostWarningWaitTime	0x6
#define GbtErrPause_SUPPORT	1
#define MICROCODE_BLOCK_SIZE	0x800
#define PACK_MICROCODE	1
#define FV_MICROCODE_BASE	0xffee0000
#define FV_MICROCODE_UPDATE_BASE	0xff850000
#define SPS_ME_SUPPORT	1
#define ME_SERVER_SUPPORT	1
#define ME_PLATFORM_SUPPORT	1
#define ME_MAJOR_REV	0x1
#define ME_MINOR_REV	0x0
#define HECI1_BUS	0x0
#define HECI1_DEVICE	0x16
#define HECI1_FUNC	0x0
#define HECI2_BUS	0x0
#define HECI2_DEVICE	0x16
#define HECI2_FUNC	0x1
#define KT_DEVICE	0x16
#define KT_FUNC	0x3
#define JAKETOWN_OEM_ROL_CTRL	0
#define DENLOW_NOTIFICATION	1
#define TCPU	0x1
#define HECI_SUPPORT	1
#define ME_CORE_SUPPORT	1
#define CPU_PSTATE_INFO_SUPPORT	1
#define IntelGigabitLan_SUPPORT	1
#define IPMI_SUPPORT	1
#define USE_PLATFORM_EVENT_MESSAGE	0
#define BMC_ACPI_SWSMI	0xc0
#define BMC_ACPI_SWSMI_MAX	0xc6
#define BSMI	0xc0
#define KCS_INTERFACE	0x1
#define BT_INTERFACE	0x2
#define IPMI_SYSTEM_INTERFACE	0x1
#define IPMI_KCS_BASE_ADDRESS	0xca2
#define IPMI_BT_BASE_ADDRESS	0xe4
#define BT_DELAY	0x4e400
#define IPMI_KCS_DATA_PORT	0xca2
#define IPMI_KCS_COMMAND_PORT	0xca3
#define BMC_ADDRESS_DECODE_MASK	0xc
#define BMC_INIT_DELAY	1
#define IPMI_PEI_KCS_COMMAND_PORT_READ_RETRY_COUNTER	0x3e8
#define IPMI_KCS_COMMAND_PORT_READ_RETRY_COUNTER	0x3e8
#define IPMI_SMM_KCS_COMMAND_PORT_READ_RETRY_COUNTER	0x1e
#define IPMI_KCS_DELAY_PER_RETRY	(5 * 1000)/15
#define MAX_BMC_CMD_FAIL_COUNT	0xa
#define OEM_SEL_SUPPORT	1
#define IPMI_SEPARATE_DXE_SMM_INTERFACES	0
#define BMC_TIMEZONE_SUPPORT	0
#define FRU_SMBIOS_BINARY_TYPE_CODE_SUPPORT	0
#define OEM_MANF_ID	0x51ee
#define FRU_DEVICE_ID	0xff
#define Gbt_Fru2Type2	0x1
#define Gbt_Fru2Type3	0x1
#define ServerMgmtSetup_SUPPORT	1
#define SERVER_MGMT_SETUP_DATA_LAYOUT_OVERRIDE_SUPPORT	0
#define Smbios_TSE_Full_Screen_Description_Column_Width	0x20
#define Smbios_TSE_Small_Screen_Description_Column_Width	0x18
#define IScsi_SUPPORT	1
#define EMUL6064_SUPPORT	1
#define UHCI_EMUL_SUPPORT	1
#define OHCI_EMUL_SUPPORT	0
#define ICH10_WORKAROUND	0
#define IRQ_EMUL_SUPPORT	1
#define EMULATION_ACPI_ENABLE_DISPATCH	0
#define LEGACYSREDIR_SUPPORT	1
#define DISPLAY_WHOLE_SCREEN	0
#define TRAP_INT10_WORKAROUND	0
#define SERIAL_READ_WRITE_CALLBACK	0
#define LEGACY_SREDIR_SWSMI	0x41
#define COM_MMIO_WIDTH	0x4
#define CTRLI_KEY_MAPPING	1
#define CTRLH_KEY_MAPPING	1
#define CHECK_FOR_LOOPBACK_DEVICE	0
#define CLEAR_LEGACYSREDIR_KB_BUFFER_AT_READYTOBOOT	0
#define LEGACY_TO_EFI_BOOT_SUPPORT	0
#define LEGACY_TO_EFI_TSE_SUPPORT	0
#define NetBootHotKey_SUPPORT	1
#define MFT_RUN_LIST_SIZE	0x100
#define FILE_RUN_LIST_SIZE	0x80
#define DIRECTORTY_ENTRIES_CACHED	0x64
#define MFT_CACHE_SIZE	0x4000
#define DIR_CACHE_SIZE	0x8000
#define NVMe_SUPPORT	1
#define NVME_VERBOSE_PRINT	0x0
#define NVME_SETUP	0x1
#define NVME_BUS_DRIVER_VERSION	0x1
#define NvmeController_SUPPORT	1
#define NVME_INIT_SMM_SWSMI	0x45
#define NVMEINT13_SUPPORT	1
#define NVME_SWSMI	0x42
#define NvramSmiSupport	1
#define NVRAM_SMI_FULL_PROTECTION	0
#define OemActivation_SUPPORT	0
#define SmmOemActivation_SUPPORT	0
#define OpalSecurity_SUPPORT	1
#define TPer_LOCK_ON_RESET	0
#define Disable_ME_SW_SMI	0x29
#define OFBD_SW_SMI_VALUE	0x26
#define DEF_CFG_SAMPLE_TEST	0
#define OEM_SETUP_SAMPLE_TEST	1
#define OEM_DMI_SAMPLE_TEST	1
#define Desktop_Platform	0x0
#define Mobile_Platform	0x1
#define UpServer_Platform	0x2
#define FlavorMobile	0x1
#define FlavorDesktop	0x2
#define FlavorUpServer	0x3
#define FlavorWorkStation	0x4
#define FlavorPlatformMax	0x6
#define BoardIdGraysReef	0x1
#define BoardIdFlatheadRock	0x2
#define BoardIdBaskingRidge	0x3
#define BoardIdWalnutCanyon	0x4
#define BoardIdWhiteTipMountain1	0x20
#define BoardIdWhiteTipMountain2	0x22
#define BoardIdSawtoothPeak	0x24
#define BoardIdFlatheadCreekCrb	0x31
#define BoardIdSHBDTRefresh	0x4a
#define BoardIdPearlValley	0x80
#define BoardIdRubyValley	0x82
#define DeviceID1	0x100
#define DeviceID2	0x400
#define DeviceID3	0x300
#define DeviceID4	0x301
#define DeviceID5	0x302
#define DeviceID6	0x303
#define DeviceID7	0x304
#define DeviceID8	0x305
#define ValidDeviceIDs	0x8
#define PlatformInfo_RevisonId	0x1
#define PlatformInfo_PlatformFlavor	0x2
#define PlatformInfo_BoardId	0x1
#define PlatformInfo_BoardRev	0x0
#define PlatformAcpiTables_SUPPORT	1
#define PLDN	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
#define PLDV	0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
#define PLDR	0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
#define HS01_PLD	0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0x0C, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00
#define HS02_PLD	0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0x0C, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00
#define HS03_PLD	0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00
#define PL23	0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x0C, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00
#define HS04_PLD	0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00
#define PL24	0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x0C, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00
#define HS05_PLD	0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x80, 0x02, 0x00, 0x00, 0x00, 0x00
#define PL25	0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x80, 0x02, 0x00, 0x00, 0x00, 0x00
#define HS06_PLD	0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00
#define PL26	0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00
#define HS07_PLD	0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00
#define PL27	0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x0C, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00
#define HS08_PLD	0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00
#define PL28	0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x0C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00
#define HS09_PLD	0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x80, 0x04, 0x00, 0x00, 0x00, 0x00
#define HS0A_PLD	0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00
#define HS0B_PLD	0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x31, 0x1C, 0x80, 0x05, 0x00, 0x00, 0x00, 0x00
#define HS0C_PLD	0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x31, 0x1C, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00
#define HS0D_PLD	0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x31, 0x1C, 0x80, 0x06, 0x00, 0x00, 0x00, 0x00
#define HS0E_PLD	0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x31, 0x1C, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00
#define PL2E	0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1C, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00
#define HS0F_PLD	0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1C, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00
#define PL2F	0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1C, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00
#define PLDG	0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC8, 0x00, 0xA0, 0x00
#define PLDH	0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF
#define PLDI	0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x01, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF
#define AcpiAslWrap_SUPPORT	1
#define CPPC_SUPPORT	1
#define Dptf_SUPPORT	0
#define DptfAcpiTablesLlama_SUPPORT	0
#define DptfAcpiTablesFfrd_SUPPORT	0
#define DptfAcpiTablesSds_SUPPORT	0
#define ACPIDEBUG_SUPPORT	1
#define PTID_SUPPORT	1
#define THERMAL_SUPPORT	1
#define SSDTTHERMALSDS_SUPPORT	0
#define RTD3_SUPPORT	0
#define IntelRMT_SUPPORT	0
#define INTELSENSORHUBAPP_SUPPORT	0
#define IntelRefVerDisplay_SUPPORT	1
#define PlatformSetupInfo_SUPPORT	1
#define INTEL_FVI_STRING_MEMORY_BUFF	0x100
#define INTEL_FVI_STRUCT_MAX_NUMBER	0xa
#define EfiCombineImage	0
#define LPIT_SUPPORT	1
#define LPIT_GUID	{0x9dd795eb, 0x41e8, 0x4591, 0x8e, 0x63, 0x5e, 0xf4, 0xaa, 0x33, 0xb9, 0x8}
#define RsdpPlusCsmOn_SUPPORT	1
#define SecureBoot_SUPPORT	1
#define SECURE_BOOT_MODULE_REVISION	0x17
#define DEFAULT_SECURE_BOOT_MODE	1
#define DEFAULT_PROVISION_SECURE_VARS	0
#define SET_SECURE_VARS	1
#define ALWAYS_INSTALL_DEFAULT_RT_KEYS	0
#define AuthVariable_SUPPORT	1
#define USER_MODE_POLICY_OVERRIDE	1
#define ImageVerification_SUPPORT	1
#define ENABLE_IMAGE_EXEC_POLICY_OVERRIDE	0
#define LOAD_FROM_FV	0x0
#define LOAD_FROM_OROM	0x4
#define LOAD_FROM_REMOVABLE_MEDIA	0x4
#define LOAD_FROM_FIXED_MEDIA	0x4
#define INSTALL_DUMMY_SECURITY_PROTOCOL	0
#define SecureMod_SUPPORT	1
#define SECURE_FLASH_MODULE_REVISION	0x10
#define FWCAPSULE_CERT_FORMAT	0x0
#define FWCAPSULE_IMAGE_ALLIGN	0x1000
#define FWCAPSULE_MAX_HDR_SIZE	0x1000
#define FWCAPSULE_IMAGE_SIZE	0x801000
#define FWSIG_PADDING	0x1
#define SecFlashUpd_SUPPORT	1
#define FlashUpdatePolicy	0x7
#define BBUpdatePolicy	0x7
#define IGNORE_RUNTIME_UPDATE_IMAGE_REVISION_CHECK	1
#define RUNTIME_SECURE_UPDATE_FLOW	0
#define FWCAPSULE_RECOVERY_SUPPORT	1
#define FWCAPSULE_2_0_SUPPORT	1
#define FLASH_LOCK_EVENT_NOTIFY	1
#define SecSMIFlash_SUPPORT	1
#define INSTALL_SECURE_FLASH_SW_SMI_HNDL	0
#define NEW_BIOS_MEM_ALLOC	0x1
#define SwSmi_LoadFwImage	0x1d
#define SwSmi_GetFlashPolicy	0x1e
#define SwSmi_SetFlashMethod	0x1f
#define Terminal_SUPPORT	1
#define SERIALIO_PCI_SERIAL_SUPPORT	0
#define DISABLE_TERMINAL_FOR_SCT_TEST	0x0
#define TOTAL_SERIAL_PORTS	0x2
#define PCI_SERIAL_MMIO_WIDTH	0x1
#define MAX_SIO_SERIAL_PORTS	0xa
#define MAX_PCI_SERIAL_PORTS	0x4
#define PCI_SERIAL_PORT_INDEX_BASE	0x0
#define PCI_SERIAL_PORT_0_INDEX	0x2
#define PCI_SERIAL_PORT_1_INDEX	0x3
#define PCI_SERIAL_PORT_2_INDEX	0x4
#define PCI_SERIAL_PORT_3_INDEX	0x5
#define UART_DEFAULT_BAUD_RATE	0x1c200
#define UART_DEFAULT_BAUD_RATE_INDEX	0x7
#define UART_DEFAULT_DATA_BITS	0x8
#define UART_DEFAULT_PARITY	0x1
#define UART_DEFAULT_STOP_BITS	0x1
#define UART_DEFAULT_FLOW_CONTROL	0x0
#define UART_DEFAULT_LOOPBACK_ENABLE	0x0
#define PCI_UART_INPUT_CLOCK	0x1c2000
#define COM1_DEFAULT_CONSOLE_REDIRECTION_ENABLE	0
#define COM2_DEFAULT_CONSOLE_REDIRECTION_ENABLE	0
#define COM3_DEFAULT_CONSOLE_REDIRECTION_ENABLE	0
#define COM4_DEFAULT_CONSOLE_REDIRECTION_ENABLE	0
#define COM5_DEFAULT_CONSOLE_REDIRECTION_ENABLE	0
#define COM6_DEFAULT_CONSOLE_REDIRECTION_ENABLE	0
#define COM7_DEFAULT_CONSOLE_REDIRECTION_ENABLE	0
#define COM8_DEFAULT_CONSOLE_REDIRECTION_ENABLE	0
#define COM9_DEFAULT_CONSOLE_REDIRECTION_ENABLE	0
#define PCI0_DEFAULT_CONSOLE_REDIRECTION_ENABLE	0
#define PCI1_DEFAULT_CONSOLE_REDIRECTION_ENABLE	0
#define PCI2_DEFAULT_CONSOLE_REDIRECTION_ENABLE	0
#define PCI3_DEFAULT_CONSOLE_REDIRECTION_ENABLE	0
#define DEFAULT_DEBUGGER_CONSOLE_REDIRECTION_ENABLE	1
#define DEFAULT_ACPI_SPCR_COM_PORT	0x0
#define DEFAULT_TERMINAL_TYPE	0x3
#define VTUTF8_ENABLE	1
#define RECORDER_MODE_ENABLE	0
#define DEFAULT_ACPI_SPCR_TABLE_TERMINAL_TYPE	0x2
#define HARDWARE_FLOW_CONTROL_SETUP_OPTION	0x1
#define MAX_FAILURES_ALLOWED	0x5
#define SOFTWARE_FLOW_CONTROL_SETUP_OPTION	0x2
#define TIMEOUT_FOR_DETERMINING_LONE_ESC_CHAR	0x989680
#define NUMBER_OF_TIME_FOR_ESC_SEQUENCE_CHECKING	0x14
#define SPCR_ACPI_OEM_ID	A M I 
#define SPCR_ACPI_OEM_TBL_ID	APTIO4
#define UART_FIFO_SIZE	0x10
#define REFRESH_SCREEN_KEY	0x12
#define ASCII_CONTROL_CODE_SUPPORT	1
#define spcr_interface_type	0x0
#define spcr_addr_spc_id	0x1
#define spcr_addr_bit_width	0x8
#define spcr_addr_bit_offset	0x0
#define spcr_access_size	0x0
#define spcr_interrupt_type	0x5
#define spcr_global_system_int	0x3
#define spcr_parity	0x0
#define spcr_stop_bits	0x1
#define spcr_pci_device_id	0xffff
#define spcr_pci_vendor_id	0xffff
#define spcr_pci_bus_number	0x0
#define spcr_pci_device_number	0x0
#define spcr_pci_function_number	0x0
#define spcr_pci_flags	0x0
#define spcr_pci_segment	0x0
#define SERIAL_WRITE_ERROR_CHECK	1
#define MAXIMUM_SERIAL_WRITE_ERROR_COUNT	0xa
#define CLEAR_TERMINAL_KB_BUFFER_AT_READYTOBOOT	0
#define OEM_ESC_SEQUENCES	1
#define PUTTY_VT100	0x1
#define PUTTY_LINUX	0x2
#define PUTTY_XTERMR6	0x4
#define PUTTY_SCO	0x8
#define PUTTY_ESCN	0x10
#define PUTTY_VT400	0x20
#define INSTALL_LEGACY_OS_THROUGH_REMOTE	0
#define DONT_SEND_ASCII_CONTROL_PRINTABLE_CHARACTERS	0
#define DISABLE_PCI_REDIRECTION_ON_ACPI_ENABLE_DISABLE	0
#define SERIAL_MOUSE_DETECTION	0
#define Shell_SUPPORT	1
#define SMBIOS_SUPPORT	1
#define AMI_SMBIOS_MODULE_VERSION	0x69
#define EFI_SMBIOS_PROTOCOL_GUID	{0x03583ff6, 0xcb36, 0x4940, 0x94, 0x7e, 0xb9, 0xb3, 0x9f, 0x4a, 0xfa, 0xf7}
#define SMBIOS_TABLE_LOCATION	0x1
#define SMBIOS_DMIEDIT_DATA_LOC	0x0
#define ADD_STRUCTURE_LOCATION	1
#define WRITE_STRUCTURE_HANDLE_POLICY	0
#define SMBIOS_UPDATE_POLICY	0
#define UPDATE_BASEBOARD_TYPE2	0
#define UPDATE_SYSTEM_CHASSIS_TYPE3	0
#define UPDATE_CPU_TYPE4	1
#define UPDATE_SLOT_TYPE9	1
#define UPDATE_MEMORY_TYPE16	1
#define DYNAMIC_UPDATE_TYPE0_EC_VERSION	1
#define SMBIOS_DYNAMIC_UPDATE_POLICY	0
#define NUMBER_OF_SYSTEM_CHASSIS	0x1
#define ELEMENT_COUNT_1	0x0
#define ELEMENT_COUNT_2	0x2
#define ELEMENT_COUNT_3	0x3
#define ELEMENT_COUNT_4	0x4
#define ELEMENT_COUNT_5	0x5
#define ELEMENT_LEN_1	0x0
#define ELEMENT_LEN_2	0x3
#define ELEMENT_LEN_3	0x3
#define ELEMENT_LEN_4	0x3
#define ELEMENT_LEN_5	0x3
#define CONT_ELEMENT	{0,0,0}
#define CONT_ELEMENT_1	{0,0,0}
#define CONT_ELEMENT_2	{0,0,0,0,0,0}
#define CONT_ELEMENT_3	{0,0,0,0,0,0,0,0,0}
#define CONT_ELEMENT_4	{0,0,0,0,0,0,0,0,0,0,0,0}
#define CONT_ELEMENT_5	{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}
#define PROCESSOR_DMIEDIT_SUPPORT	1
#define SmbiosDMIEdit_SUPPORT	1
#define NonSmiDmiEdit_Support	1
#define DMI_ARRAY_COUNT	0x100
#define SmbiosFlashData_SUPPORT	1
#define FLASHDATA_SIZE	0x800
#define SMI_FLASH_INTERFACE_VERSION	0xb
#define REPORT_NCB_BY_ROM_LAYOUT	0
#define PRESERVE_PASSWORDS	0
#define PRESERVE_EFIBOOTORDER	1
#define AFU_BUFFER_IN_SHADOW	0
#define NON_SECURE_NCB_UPDATE	0
#define RECOVERY_PRESERVE_VARS_IN_SMM	1
#define RECOVERY_PRESERVE_ROMHOLE	1
#define BACKUP_NVRAM_WHEN_FLASH	0
#define SMM_SUPPORT	1
#define SMM_MAJOR_VER	0x0
#define SMM_MINOR_VER	0x51
#define SMM_THUNK_NO_AB_SEG	1
#define SMM_THUNK_IN_CSM	0
#define SMM_TIME_OUT_US	0x3e8
#define BSP_SMM_STACK_SIZE	0x4000
#define AP_SMM_STACK_SIZE	0x4000
#define LOAD_SMM_DRIVERS_IN_TSEG_OUTSIDE_SMM	0
#define INTEL_MP_SW_SMI_PATCH	0
#define SMM_COMM_SW_SMI	0xdd
#define SMM_PI_INCLUDES_SUPPORT	1
#define SMM_PI_PROTOCOLS_SUPPORT	1
#define STRING_STATUS_SUPPORT	1
#define DATAHUB_STATUS_SUPPORT	1
#define CHECKPOINT_PROGRESS_CODES_MAP	ProgressCheckpointMap
#define CHECKPOINT_ERROR_CODES_MAP	ErrorCheckpointMap
#define BEEP_PROGRESS_CODES_MAP	ProgressBeepMap
#define BEEP_ERROR_CODES_MAP	ErrorBeepMap
#define STATUS_CODE_VERSION	0x10
#define TCG2Support	1
#define SecurityChipMode	0x7
#define TPM12Enabled	0x4
#define TPM20Enabled	0x1
#define FTPM20Enabled	0x2
#define TCG_LEGACY	0
#define TCGPPISPEC_1_2_SUPPORT	1
#define USE_BIOS_IMAGE_AS_CRTM	0
#define WORD_ACCESS_SMI_PORT	0
#define StartupCmd_SelfTest_State	1
#define OVERRIDE_TCG_ASL	0
#define Stack_Work_Around	0x0
#define PMBASE_RTC_WKAround	0x1
#define SET_LIFETIME_PPLOCK	0
#define USE_ZERO_SEPARATOR	0
#define CID_SUPPORT	0
#define PORT_TPM_IOMEMBASE	0xfed40000
#define TCG_PCCLIENT_SPEC	0
#define TPM_IOBASE	0x600
#define TPM_IOBASE_MAX	0x6ff
#define TPM_IOBASE2	0x7e
#define TPM_IOBASE2_DATA	0x7f
#define TPM_IOSZ	0xff
#define TCGSMIPORT	0xb2
#define TCGSMIDATAPORT	0xb3
#define PPI_OFFSET	0x35
#define PARTIALLY_MEASURE_FVMAIN	0
#define TCG_CONVENTIONAL_BIOS_6_1	1
#define TCG_MOR	1
#define TPM_PASSWORD_AUTHENTICATION	0
#define CONFIRM_SETUP_CHANGE	0
#define LOG_EV_EFI_ACTION	0
#define TCG_CLEAR_REQUEST_KEY	SCAN_F12
#define TCG_CONFIGURATION_ACCEPT_KEY	SCAN_F10
#define TCG_CONFIGURATION_IGNORE_KEY	SCAN_ESC
#define DSDT_GUID	{0x11D8AC35,0xFB8A,0x44d1,0x8D,0x09,0x0B,0x56,0x06,0xD3,0x21,0xB9}
#define MEMORY_ONLY_RESET_CONTROL_GUID	{0xe20939be, 0x32d4, 0x41be, 0xa1, 0x50, 0x89, 0x7f, 0x85, 0xd4, 0x98, 0x29}
#define CRTM_GUID	{0x546BFB1E,0x1D0C,0x4055,0xA4,0xAD,0x4E,0xF4,0xBF,0x17,0xB8,0x3A}
#define AMI_OS_PPI_CONFIRMATION_OVERRIDE_GUID	{0x5f171f5f, 0x8385, 0x4086, 0xa6, 0x9b, 0x1f, 0xcf, 0x6, 0xae, 0x4a, 0x3d}
#define AMI_BIOSPPI_FLAGS_MANAGEMENT_GUID	{0xe9008d70, 0x2a4e, 0x47ea, 0x8e, 0xc4, 0x72, 0xe2, 0x57, 0x67, 0xe5, 0xef}
#define TCG_PLATFORM_CLASS	0x0
#define TCG_BIOS_TYPE_INTERFACE	0x3
#define TCG_BIOS_TYPE_MAPPING	0x2
#define TCG_SPEC_VERSION_MAJOR	0x1
#define TCG_SPEC_VERSION_MINOR	0x2
#define TCG_SPEC_ERRATA	0x1
#define AUTO_ACCEPT_PPI	1
#define TCMF	0x0
#define TMF1	0x0
#define TMF2	0x0
#define TMF3	0x0
#define TTPF	0x1
#define TTDP	0x0
#define PTTHciSmm_SUPPORT	0
#define TPM12_SUPPORT	1
#define TPM_DRIVER_WAIT	0x5
#define DELAY_AMOUNT	0xa
#define AmiTcmLib_SUPPORT	1
#define SUPPORTED_TCM_DEVICE_1_VID	0x19f5
#define SUPPORTED_TCM_DEVICE_1_DID	0x1
#define SUPPORTED_TCM_DEVICE_2_VID	0x1b4e
#define SUPPORTED_TCM_DEVICE_2_DID	0x1
#define NUMBER_OF_SUPPORTED_TCM_DEVICES	0x2
#define TPM20CRB_SUPPORT	1
#define FTpmPlatformProfile	0
#define TPM20_CRBBASE	0xfed70000
#define TcgPeiSupport	1
#define TcgDxeSupport	1
#define AMI_TCG_BINARIES	1
#define AMI_TCG_NVFLAG_SAMPLE_SUPPORT	1
#define NV_DATA_SIZE	0xa
#define NO_PPI_PROVISION_DEFAULT	0x1
#define NO_PPI_CLEAR_DEFAULT	0x0
#define NO_PPI_MAINTENANCE_DEFAULT	0x0
#define TCG_SIZE	0x10000
#define DONT_SEND_SELFTEST_TILL_READY_TO_BOOT	1
#define SELF_TEST_VID	0x15d1
#define Measure_Boot_Data	0
#define PPI_DISPLAY_OFFSET	0x1
#define Measure_Smbios_Tables	0
#define TCGMeasureSecureBootVariables	1
#define UnconfiguredSecureBootVariables	0
#define MEASURE_CRTM_VERSION_PEI_FUNCTION	MeasureCRTMVersion
#define MEASURE_TCG_PCCLIENT_ID_PEI_FUNCTION	MeasureTCGPcClientSpecID
#define MEASURE_CORE_DXE_FW_VOL_PEI_FUNCTION	MeasureDxeCoreFwVol
#define MEASURE_PCI_OPTION_ROM_DXE_FUNCTION	MeasurePCIOproms
#define MEASURE_HANDOFF_TABLES_DXE_FUNCTION	MeasureHandoffTables
#define MEASURE_CPU_MICROCODE_DXE_FUNCTION	MeasureCpuMicroCode
#define MEASURES_TCG_BOOT_SEPARATORS_DXE_FUNCTION	MeasureSeparators
#define MEASURE_SECURE_BOOT_DXE_FUNCTION	MeasureSecurebootVariables
#define MEASURES_BOOT_VARIABLES_DXE_FUNCTION	MeasureAllBootVariables
#define MEASURE_WAKE_EVENT_DXE_FUNCTION	MeasureWakeEvent
#define SKIP_PHYSICAL_PRESENCE_LOCK_FUNCTION	DummySkipPhysicalPresence
#define SMBIOS_VER_32	0
#define TcgLegacy_SUPPORT	1
#define TCG_MOR_REG	0xe3
#define DISPLAY_TPM_SETUP_ERROR	0
#define TPMCLEARONROLLBACK_SUPPORT	1
#define Tpm20PlatformSupport	1
#define TPMF	0x0
#define TSE_MAJOR	0x02
#define TSE_MINOR	0x17
#define TSE_BUILD	0x1246
#define SETUP_BMP_LOGO_SUPPORT	1
#define SETUP_GIF_LOGO_SUPPORT	0
#define SETUP_JPEG_LOGO_SUPPORT	0
#define SETUP_PCX_LOGO_SUPPORT	0
#define SETUP_PNG_LOGO_SUPPORT	0
#define SETUP_OEM_FORMAT_LOGO_SUPPORT	0
#define SETUP_GRAYOUT_READONLY_CONTROL	0
#define MAX_POST_GC_MODE	{ 0, 80, 25, 0, 0 }
#define TSE_DEBUG_MESSAGES	0x0
#define SUPPRESS_PRINT	1
#define SERIAL_DEBUG	1
#define SETUP_PRINT_ENTER_SETUP_MSG	1
#define SETUP_PRINT_ENTER_BBSPOPUP_MSG	1
#define SETUP_ALT_ENTRY_SHIFT_STATE	0
#define TSE_ANSI_ESC_CODE_SUPPORT	0x0
#define POPUP_MENU_ENTRY_SHIFT_STATE	0
#define SETUP_OEM_KEY2_ENABLE	0
#define SETUP_OEM_KEY3_ENABLE	0
#define SETUP_OEM_KEY4_ENABLE	0
#define TSE_BOOT_ONLY_SPLASH_LOGO_SUPPORT	1
#define SETUP_RUNTIME_IFR_PROCESSING	1
#define TSE_HOOKBASE_VALUE	0xFFFF0000
#define SETUP_PASSWORD_LENGTH	0x14
#define MAX_MSGBOX_WIDTH	0x2d
#define WIDE_GLYPH_SUPPORT	1
#define SETUP_DEFAULT_TIMEOUT	0xa
#define SETUP_TIMEOUT_IN_TENTHOFSEC	0
#define TSE_FOR_64BIT	1
#define TSE_CSM_SUPPORT	1
#define PROGRESSBAR_BACKGROUNDCOLOR	{0,0,0,0}
#define PROGRESSBAR_BORDERCOLOR	{0xc0,0xc0,0xc0,0}
#define PROGRESSBAR_FILLCOLOR	{0xc0,0xc0,0xc0,0}
#define SETUP_SHOW_ALL_BBS_DEVICES	0
#define TSE_DEVICE_PATH_NAME	0
#define TSE_BOOT_NOW_IN_BOOT_ORDER	0
#define TSE_CLEAR_USERPW_WITH_ADMINPW	0
#define SETUP_USE_AMI_DEFAULTS	1
#define TSE_LOAD_PASSWORD_ON_DEFAULTS	0
#define MINISETUP_MOUSE_SUPPORT	0
#define SINGLE_CLICK_ACTIVATION	0
#define SETUP_STORE_KEYCODE_PASSWORD	0x0
#define STYLE_DATE_FORMAT	0x0
#define STYLE_SHOW_DAY	1
#define SETUP_USER_PASSWORD_POLICY	1
#define SETUP_SUPPORT_ADD_BOOT_OPTION	0
#define SETUP_SUPPORT_ADD_DRIVER_OPTION	0
#define SETUP_ENTRY_LEGACY_CODE	0x53
#define SETUP_ALT_ENTRY_LEGACY_CODE	0x3c
#define POPUP_MENU_ENTRY_LEGACY_CODE	0x41
#define SETUP_OEM_KEY1_EFIKEY	0x5F
#define SETUP_OEM_KEY1_TOGGLE	0x00
#define SETUP_SUPPORT_KEY_MONITORING	0
#define SETUP_STORE_EFI_KEY_PASSWORD	0
#define TSE_CAPITAL_BOOT_OPTION	1
#define PASSWORD_WITH_SPECIAL_CHAR_SUPPORT	1
#define SETUP_LINK_HISTORY_SUPPORT	1
#define SETUP_DISPLAY_SUBMENU_PAGETITLE	0
#define SETUP_GROUP_DYNAMIC_PAGES	1
#define SETUP_ORPHAN_PAGES_AS_ROOT_PAGE	0
#define SETUP_ITK_COMPATIBILITY	0
#define NO_VARSTORE_SUPPORT	0
#define TSE_CONTINUE_BOOT_NOW_ON_FAIL	1
#define SETUP_UPDATE_BOOT_ORDER_CURSOR	0
#define TSE_PRESERVE_DISABLED_BBS_DEVICE_ORDER	0
#define TSE_BOOT_TIME_OUT_AS_ZERO	0
#define TSE_SAVE_DISABLED_BBS_DEVICEPATH	1
#define TSE_POSTSCREEN_SCROLL_AREA	{0,0,24,80}
#define TSE_USE_OEM_ACTION_READ_KEY	0
#define SECONDARY_BOOT_FROM_ENABLED_DEVICES	0
#define AMITSE_SUBPAGE_AS_ROOT_PAGE_LIST_SUPPORT	0
#define AMITSE_HIDE_ROOT_PAGE	0
#define OVERRIDE_CheckIsAllowedPasswordChar	0
#define OVERRIDE_PopupPasswordFormCallback	0
#define OVERRIDE_PopupPwdHandleActionOverRide	0
#define OVERRIDE_PasswordCheckInstalled	0
#define OVERRIDE_PasswordAuthenticate	0
#define OVERRIDE_PasswordUpdate	0
#define OVERRIDE_PasswordCommitChanges	0
#define OVERRIDE_PopupPasswordCheckInstalled	0
#define OVERRIDE_PopupPasswordAuthenticate	0
#define OVERRIDE_NoVarStoreSupport	0
#define OVERRIDE_NoVarStoreUpdateSystemAccess	0
#define OVERRIDE_ItkSupport	0
#define OVERRIDE_BbsItkBoot	0
#define OVERRIDE_GetAMITSEVariable	0
#define OVERRIDE_GetBootTimeOut	0
#define OVERRIDE_VarBuildItkDefaults	0
#define OVERRIDE_SetSystemAccessValueItk	0
#define OVERRIDE_FindVarFromITKQuestionId	0
#define OVERRIDE_IsOEMLogoType	0
#define OVERRIDE_ConvertOEMFormatToUgaBlt	0
#define OVERRIDE_CleanUpOEMLogo	0
#define OVERRIDE_DoOEMLogoAnimate	0
#define OVERRIDE_BBSBuildName	0
#define OVERRIDE_BBSGetNonStandardGroupType	0
#define OVERRIDE_FramePwdCallbackIdePasswordUpdate	0
#define OVERRIDE_PopupPwdAuthenticateIDEPwd	0
#define OVERRIDE_PopupPwdUpdateIDEPwd	0
#define OVERRIDE_TSEIDEPasswordGetName	0
#define OVERRIDE_TSEIDEPasswordAuthenticate	0
#define OVERRIDE_TSEIDEPasswordUpdate	0
#define OVERRIDE_TSEIDEPasswordGetDataPtr	0
#define OVERRIDE_TSEIDEPasswordGetLocked	0
#define OVERRIDE_TSEIDEPasswordCheck	0
#define OVERRIDE_TSEIDEPasswordFreezeDevices	0
#define OVERRIDE_TSEUnlockHDD	0
#define OVERRIDE_TSESetHDDPassword	0
#define OVERRIDE_TSEIDEUpdateConfig	0
#define OVERRIDE_OEMSpecialGetControlCount	0
#define OVERRIDE_OEMSpecialOneOfFixup	0
#define OVERRIDE_OEMSpecialUpdateOneOf	0
#define OVERRIDE_OEMSpecialGotoFixup	0
#define OVERRIDE_OEMSpecialGotoSelect	0
#define OVERRIDE_TSEMouseInitHook	0
#define OVERRIDE_TSEMouseStopHook	0
#define OVERRIDE_TSEMouseDestoryHook	0
#define OVERRIDE_TSEMouseRefreshHook	0
#define OVERRIDE_TSEMouseStartHook	0
#define OVERRIDE_TSEMouseIgnoreMouseActionHook	0
#define OVERRIDE_TSEStringReadLoopEntryHook	0
#define OVERRIDE_TSEStringReadLoopExitHook	0
#define OVERRIDE_GetMessageboxColorHook	0
#define OVERRIDE_GOPSetScreenResolutionHook	0
#define OVERRIDE_LaunchHotKeyBootOption	0
#define OVERRIDE_DriverHealthSystemReset	0
#define OVERRIDE_UefiBootFailHook	0
#define OVERRIDE_LegacyBootFailHook	0
#define OVERRIDE_UpdateNumericDisplayString	0
#define OVERRIDE_MainSetupLoopHook	0
#define OVERRIDE_MainSetupLoopInitHook	0
#define OVERRIDE_ProcessBrowserActionRequestHook	0
#define OVERRIDE_OEMCheckControlCondition	0
#define OVERRIDE_GetUefiSpecVersion	0
#define OVERRIDE_TSEMouseInit	0
#define OVERRIDE_TSEMouseStop	0
#define OVERRIDE_TSEIsMouseClickedonSoftkbd	0
#define OVERRIDE_TSEMouseRefresh	0
#define OVERRIDE_TSEMouseStart	0
#define OVERRIDE_TSEMouseFreeze	0
#define OVERRIDE_TSEGetCoordinates	0
#define OVERRIDE_TSEMouseReadInfo	0
#define OVERRIDE_TSEMouseDestroy	0
#define OVERRIDE_TSEGetactualScreentop	0
#define OVERRIDE_TSENumericSoftKbdInit	0
#define OVERRIDE_TSENumericSoftKbdExit	0
#define OVERRIDE_LaunchSecondaryBootPath	0
#define OVERRIDE_OsUpdateCapsuleWrap	0
#define OVERRIDE_UIUpdateCallbackHook	0
#define OVERRIDE_FixMergePagesExtraHook	0
#define OVERRIDE_PageRemoveHook	0
#define OVERRIDE_ProcessPackNotificationHook	0
#define OVERRIDE_CsmBBSBootOptionName	0
#define MSGBOX_PROGRESS_BAR_SEGMENT_COUNT	0x14
#define CONTRIB_BGRT_TABLE_TO_ACPI	0x1
#define BIOS_SIGNON_MESSAGE2	BIOS Date: $(TODAY) $(NOW) Ver: $(PROJECT_TAG)$(PROJECT_MAJOR_VERSION)$(PROJECT_MINOR_VERSION)
#define TSE_APTIO_5_SUPPORT	0
#define TSE_USE_GETGYLPH_PRINTLENGH	0
#define TSE_LOAD_OPTION_HIDDEN	1
#define AMITSE_VERSION	Version %x.%02x.%04x.
#define BOOT_FLOW_NORMAL_LAUNCH_DEFAULT_BOOTIMAGE	1
#define BOOT_FLOW_NORMAL_INFINITE_LOOP	0
#define STYLE_HELP_AREA_SCROLLBAR	0
#define TSE_OEM_POSTLOGO_SUPPORT	0
#define TSE_ROMHOLE_MAKFILE_GUID	05ca020b-0fc1-11dc-9011-00173153eba8
#define TSE_ROMHOLE_HEADER_GUID	{0x05ca020b, 0x0fc1, 0x11dc, 0x90, 0x11, 0x00, 0x17, 0x31, 0x53, 0xeb, 0xa8}
#define ROMHOLE_BLOCK_SIZE	0x10000
#define OSIndication_SUPPORT	1
#define SETUP_DELAY_POST_TILL_GOP	1
#define DRAW_POST_LOGO_AT_0POS	0
#define TSE_IGNORE_KEY_FOR_FASTBOOT	0
#define TSE_CURSOR_SUPPORT	1
#define SUPPORT_ESRT	1
#define TSE_SUPPORT_NATIVE_RESOLUTION	1
#define BOOT_OVERRIDE_BOOTNEXT_VARIABLE_FEATURE	0
#define TSE_SUPPRESS_MULTILINE_FOR_ONEOFLABEL	0
#define SETUP_SAVE_PSWD_TO_NVRAM	0
#define TSE_DONOT_LOAD_PASSWORD_ON_DEFAULTS	0
#define FLUSH_KEYS_AFTER_READ	1
#define TSE_LOAD_DEFAULTS_FROM_DEFAULTS_BUFFER	1
#define AMITSE_ROOT_PAGE_ORDER_SUPPORT	0
#define SETUP_ROOT_PAGE_ORDER_GUID	  { 0x9204ecbe, 0xa665, 0x49d3,  0x86, 0xde, 0x8, 0x12, 0x99, 0xe2, 0x23, 0xef }
#define SETUP_GO_TO_EXIT_PAGE_ON_EXIT_KEY	0
#define TSE_SHOW_PROMPT_STRING_AS_TITLE	0
#define TSE_DONOT_LOAD_SYSTEM_ACCESS_FOR_USER_DEFAULT	0
#define SHOW_FORMSETS_WITH_CLASSGUID	1
#define TSE_HASH_PASSWORD	0
#define AMITSE_SUPPRESS_DYNAMIC_FORMSET	0
#define SUPPRESS_HANDLE_FOR_VAR_CREATION	0
#define OVERRIDE_GetGraphicsBitMapFromFV	0
#define OVERRIDE_CheckAdvShiftState	0
#define OVERRIDE_LaunchSecBootPathFromEnabledDevs	0
#define OVERRIDE_FramePasswordAdvancedCallback	0
#define OVERRIDE_TseLaunchFileSystem	0
#define TSE_DEFAULT_SETUP_PASSWORD_SUPPORT	0
#define RT_ACCESS_SUPPORT_IN_HPKTOOL	0
#define DISABLE_ESC_IN_BBS	0
#define TSE_BOARD_SOURCE_SUPPORT	1
#define TSE_ADVANCED_BIN_SUPPORT	1
#define HII_VERSION	0x2
#define APTIO_4_00	1
#define SETUP_SUPPORT_PLATFORM_LANG_VAR	1
#define STYLE_COLOR_GRAYOUT	EFI_DARKGRAY
#define SETUP_STYLE_BIN_EZPORT	1
#define HOTCLICK_FULLSCREEN_SUPPORT	1
#define TSE_SEPERATE_EFI_LEGACY_OPTIONS	0
#define TSE_NVRAM_DEFAULTS_SUPPORT	1
#define SETUP_USE_GRAPHICS_OUTPUT_PROTOCOL	1
#define TSE_USE_EDK_LIBRARY	0
#define SETUP_OEM_SPECIAL_CONTROL_SUPPORT	0
#define SETUP_USE_GUIDED_SECTION	0
#define TSE_MAX_DRIVE_NAME	0x33
#define TSE_LITE_SOURCES_SUPPORT	1
#define POPUP_MENU_ENTER_SETUP	1
#define UEFI_HII_2_1_SUPPORT	1
#define UEFI_SOURCES_SUPPORT	1
#define UEFI_2_1_SUPPORT	1
#define TSE_SUPPORT_VFRCOMPILE_1_88	0
#define TianoHII_SUPPORT	1
#define SETUP_FORM_BROWSER_SUPPORT	1
#define SETUP_STYLE_EZPORT	1
#define TSE_STYLE_SOURCES_SUPPORT	1
#define SETUP_STYLE_FULL_SCREEN	1
#define STYLE_FULL_MAX_ROWS	(UINT8)(31)
#define STYLE_FULL_MAX_COLS	(UINT8)(100)
#define STYLE_STD_MAX_ROWS	(UINT8)(24)
#define STYLE_STD_MAX_COLS	(UINT8)(80)
#define PAGEBORDER_FULL_X	(UINT8)(0)
#define PAGEBORDER_FULL_Y	(UINT8)(2)
#define PAGEBORDER_FULL_W	(UINT8)(STYLE_FULL_MAX_COLS)
#define PAGEBORDER_FULL_H	(UINT8)(STYLE_FULL_MAX_ROWS - 3)
#define FULL_HORIZONTAL_HELP_DIVIDER	(UINT8)(STYLE_FULL_MAX_ROWS/2)
#define TITLE_FULL_X	(UINT8)(0)
#define TITLE_FULL_Y	(UINT8)(0)
#define TITLE_FULL_W	(UINT8)(STYLE_FULL_MAX_COLS)
#define TITLE_FULL_H	(UINT8)(1)
#define MENU_FULL_X	(UINT8)(0)
#define MENU_FULL_Y	(UINT8)(1)
#define MENU_FULL_W	(UINT8)(STYLE_FULL_MAX_COLS)
#define MENU_FULL_H	0x1
#define HELPTITLE_FULL_X	0x0
#define HELPTITLE_FULL_Y	(UINT8)(PAGEBORDER_FULL_Y+PAGEBORDER_FULL_H)
#define HELPTITLE_FULL_W	(UINT8)(STYLE_FULL_MAX_COLS)
#define HELPTITLE_FULL_H	0x1
#define HELP_FULL_X	(UINT8)(FULL_VERTICAL_MAIN_DIVIDER+1)
#define HELP_FULL_Y	(UINT8)(PAGEBORDER_FULL_Y+1)
#define HELP_FULL_W	(UINT8)(PAGEBORDER_FULL_W - FULL_VERTICAL_MAIN_DIVIDER-2)
#define HELP_FULL_H	(UINT8)(FULL_HORIZONTAL_HELP_DIVIDER - PAGEBORDER_FULL_Y - 2)
#define MAIN_FULL_X	(UINT8)(PAGEBORDER_FULL_X+1)
#define MAIN_FULL_Y	(UINT8)(PAGEBORDER_FULL_Y+1)
#define MAIN_FULL_W	(UINT8)(FULL_VERTICAL_MAIN_DIVIDER - 2)
#define MAIN_FULL_H	(UINT8)(PAGEBORDER_FULL_H-2)
#define NAV_FULL_X	(UINT8)(FULL_VERTICAL_MAIN_DIVIDER+1)
#define NAV_FULL_Y	(UINT8)(FULL_HORIZONTAL_HELP_DIVIDER+1)
#define NAV_FULL_W	(UINT8)(PAGEBORDER_FULL_W - FULL_VERTICAL_MAIN_DIVIDER-2)
#define NAV_FULL_H	(UINT8)(PAGEBORDER_FULL_H - FULL_HORIZONTAL_HELP_DIVIDER)
#define PAGEBORDER_X	0x0
#define PAGEBORDER_Y	0x2
#define PAGEBORDER_W	(UINT8)(STYLE_STD_MAX_COLS)
#define PAGEBORDER_H	(UINT8)(STYLE_STD_MAX_ROWS - 3)
#define VERTICAL_MAIN_DIVIDER	(UINT8)(STYLE_STD_MAX_COLS*2/3)
#define HORIZONTAL_HELP_DIVIDER	(UINT8)(STYLE_STD_MAX_ROWS/2)
#define TITLE_X	(UINT8)(0)
#define TITLE_Y	(UINT8)(0)
#define TITLE_W	(UINT8)(STYLE_STD_MAX_COLS)
#define TITLE_H	(UINT8)(1)
#define MENU_X	(UINT8)(0)
#define MENU_Y	(UINT8)(1)
#define MENU_W	(UINT8)(STYLE_STD_MAX_COLS)
#define MENU_H	0x1
#define HELPTITLE_X	0x0
#define HELPTITLE_Y	(UINT8)(PAGEBORDER_Y+PAGEBORDER_H)
#define HELPTITLE_W	(UINT8)(STYLE_STD_MAX_COLS)
#define HELPTITLE_H	0x1
#define HELP_X	(UINT8)(VERTICAL_MAIN_DIVIDER+1)
#define HELP_Y	(UINT8)(PAGEBORDER_Y+1)
#define HELP_W	(UINT8)(PAGEBORDER_W - VERTICAL_MAIN_DIVIDER-2)
#define HELP_H	(UINT8)(HORIZONTAL_HELP_DIVIDER - PAGEBORDER_Y - 1)
#define MAIN_X	(UINT8)(PAGEBORDER_X+1)
#define MAIN_Y	(UINT8)(PAGEBORDER_Y+1)
#define MAIN_W	(UINT8)(VERTICAL_MAIN_DIVIDER - 2)
#define MAIN_H	(UINT8)(PAGEBORDER_H-1)
#define NAV_X	(UINT8)(VERTICAL_MAIN_DIVIDER+1)
#define NAV_Y	(UINT8)(HORIZONTAL_HELP_DIVIDER+1)
#define NAV_W	(UINT8)(PAGEBORDER_W - VERTICAL_MAIN_DIVIDER-2)
#define NAV_H	(UINT8)(PAGEBORDER_H - HORIZONTAL_HELP_DIVIDER)
#define PAGE_BGCOLOR	(UINT8)(EFI_BACKGROUND_LIGHTGRAY)
#define PAGE_FGCOLOR	(UINT8)(EFI_BLUE)
#define MAIN_BGCOLOR	(UINT8)(PAGE_BGCOLOR)
#define MAIN_FGCOLOR	(UINT8)(PAGE_FGCOLOR)
#define TITLE_BGCOLOR	(UINT8)(EFI_BACKGROUND_BLUE)
#define TITLE_FGCOLOR	(UINT8)(EFI_WHITE)
#define MENU_BGCOLOR	(UINT8)(EFI_BACKGROUND_BLUE)
#define MENU_FGCOLOR	(UINT8)(EFI_LIGHTGRAY)
#define SELECTED_MENU_BGCOLOR	(UINT8)(EFI_BACKGROUND_LIGHTGRAY)
#define SELECTED_MENU_FGCOLOR	(UINT8)(EFI_BLUE)
#define HELP_BGCOLOR	(UINT8)(PAGE_BGCOLOR)
#define HELP_FGCOLOR	(UINT8)(PAGE_FGCOLOR)
#define HELPTITLE_BGCOLOR	(UINT8)(EFI_BACKGROUND_BLUE)
#define HELPTITLE_FGCOLOR	(UINT8)(EFI_LIGHTGRAY)
#define NAV_BGCOLOR	(UINT8)(PAGE_BGCOLOR)
#define NAV_FGCOLOR	(UINT8)(PAGE_FGCOLOR)
#define SCROLLBAR_BGCOLOR	(UINT8)(PAGE_BGCOLOR)
#define SCROLLBAR_FGCOLOR	(UINT8)(PAGE_FGCOLOR)
#define SCROLLBAR_UPARROW_BGCOLOR	(UINT8)(PAGE_BGCOLOR)
#define SCROLLBAR_UPARROW_FGCOLOR	(UINT8)(PAGE_FGCOLOR)
#define SCROLLBAR_DOWNARROW_BGCOLOR	(UINT8)(PAGE_BGCOLOR)
#define SCROLLBAR_DOWNARROW_FGCOLOR	(UINT8)(PAGE_FGCOLOR)
#define POPUP_BGCOLOR	(UINT8)(EFI_BACKGROUND_BLUE)
#define POPUP_FGCOLOR	(UINT8)(EFI_WHITE)
#define FOCUS_COLOR	(UINT8)(EFI_WHITE)
#define LABEL_FOCUS_COLOR	(UINT8)(FOCUS_COLOR)
#define CONTROL_FOCUS_COLOR	(UINT8)(FOCUS_COLOR)
#define NON_FOCUS_COLOR	(UINT8)(PAGE_FGCOLOR)
#define LABEL_NON_FOCUS_COLOR	(UINT8)(NON_FOCUS_COLOR)
#define CONTROL_NON_FOCUS_COLOR	(UINT8)(NON_FOCUS_COLOR)
#define PAGE_LINK_COLOR	(UINT8)(PAGE_FGCOLOR)
#define EDIT_BGCOLOR	(UINT8)(EFI_BACKGROUND_BLUE)
#define EDIT_FGCOLOR	(UINT8)(EFI_WHITE)
#define TEXT_COLOR	(UINT8)(EFI_DARKGRAY)
#define MEMO_COLOR	(UINT8)(EFI_BLACK)
#define FULL_STYLE_CONTROL_LEFT_MARGIN	0x25
#define FULL_STYLE_CONTROL_LEFT_PAD	0x2
#define FULL_STYLE_CONTROL_RIGHT_AREA_WIDTH	((UINT8)FULL_VERTICAL_MAIN_DIVIDER - FULL_STYLE_CONTROL_LEFT_MARGIN - FULL_STYLE_CONTROL_LEFT_PAD)
#define STYLE_CONTROL_LEFT_MARGIN	0x18
#define STYLE_CONTROL_LEFT_PAD	0x2
#define STYLE_CONTROL_RIGHT_AREA_WIDTH	((UINT8)VERTICAL_MAIN_DIVIDER - STYLE_CONTROL_LEFT_MARGIN - STYLE_CONTROL_LEFT_PAD)
#define FULL_STYLE_LABEL_LEFT_MARGIN	2
#define STYLE_LABEL_LEFT_MARGIN	2
#define STYLE_SCROLLBAR_ROLLOVER	1
#define STYLE_PAGE_FIRSTITEM_FOCUS	0
#define STYLE_SUBPAGE_FIRSTITEM_FOCUS	0
#define STYLE_HOTKEY_FAILSAFE	SCAN_F6
#define STYLE_SHADOW_SUPPORT	1
#define STYLE_SPACEKEY_INCREMENT	0x1
#define TSE_PASSWORD_ENCODE_SUPPORT	1
#define PASSWORDENCODELIB	$(BUILD_DIR)/TsePasswordEncode.lib
#define UefiNetworkStackII	1
#define Dpc_SUPPORT	1
#define Arp_SUPPORT	1
#define Snp_SUPPORT	1
#define Mnp_SUPPORT	1
#define UefiPxeBc_SUPPORT	1
#define IpSec_SUPPORT	0
#define Tcp_SUPPORT	1
#define UefiIpv4StackII_SUPPORT	1
#define Dhcp4_SUPPORT	1
#define Ip4Config_SUPPORT	1
#define Ip4_SUPPORT	1
#define Mtftp4_SUPPORT	1
#define Udp4_SUPPORT	1
#define UefiIpv6StackII_SUPPORT	1
#define Dhcp6_SUPPORT	1
#define Ip6_SUPPORT	1
#define Mtftp6_SUPPORT	1
#define Udp6_SUPPORT	1
#define AMIUSB_SUPPORT	1
#define USB_DRIVER_MAJOR_VER	0x8
#define USB_DRIVER_MINOR_VER	0xa
#define USB_DRIVER_BUILD_VER	0x1f
#define UHCI_SUPPORT	1
#define OHCI_SUPPORT	1
#define EHCI_SUPPORT	1
#define USB_HOTPLUG_FDD	0
#define USB_HOTPLUG_HDD	0
#define USB_HOTPLUG_CDROM	0
#define HIDE_USB_SUPPORT_SETUP_QUESTION	1
#define KBC_EMULATION_8MSTD_OVERRIDE	0x19
#define KEY_REPEAT_DELAY	0x2
#define KEY_REPEAT_INITIAL_DELAY	0x6
#define USB_EHCI_HANDOFF_SUPPORT	1
#define USB_S5_WAKEUP_SUPPORT	0
#define USB_DIFFERENTIATE_IDENTICAL_DEVICE_NAME	0
#define HIDE_USB_HISPEED_SUPPORT_SETUP_QUESTION	1
#define DEFAULT_USB_EMUL6064_OPTION	1
#define USB_RUNTIME_DRIVER_IN_SMM	1
#define EXTERNAL_USB_CONTROLLER_SUPPORT	1
#define USB_OHCI_HANDOFF_SUPPORT	0
#define HIDE_USB_XHCI_LEGACY_SUPPORT_SETUP_QUESTION	1
#define USB_SETUP_VARIABLE_RUNTIME_ACCESS	0
#define USB_DEV_KBD	1
#define USB_DEV_MOUSE	1
#define USB_DEV_HUB	1
#define USB_DEV_MASS	1
#define USB_DEV_POINT	1
#define MEM_PAGE_COUNT	0x8
#define USB_SEND_COMMAND_TO_KBC	0x60
#define USB_MOUSE_UPDATE_EBDA_DATA	1
#define EHCI_64BIT_DATA_STRUCTURE	1
#define EHCI_ASYNC_BELL_SUPPORT	0
#define USB_DEV_HID_COUNT	0xf
#define USB_DEV_MASS_COUNT	0x6
#define USB_DEV_CCID	1
#define USB_DEV_CCID_COUNT	0x6
#define USE_T0_T1_PROTOCOL	0x1
#define CCID_USE_INTERRUPT_INSERTION_REMOVAL	0x1
#define USB_DEV_UNSUPPORTED	0x10
#define USB_START_UNIT_BEFORE_MSD_ENUMERATION	0
#define TopDebugLevel	0x3
#define BottomDebugLevel	0x3
#define USB_SWSMI	0x31
#define USB_BEEP_ENABLE	1
#define USB_MASS_EMULATION_NATIVE	1
#define USB_MASS_EMULATION_FOR_NO_MEDIA	1
#define MAX_SIZE_FOR_USB_FLOPPY_EMULATION	0x212
#define REMOVE_USB_STORAGE_FROM_BBS_IF_NO_MEDIA	0
#define HIGHSPEED_MAX_BULK_DATA_SIZE	0x400
#define FULLSPEED_MAX_BULK_DATA_SIZE_PER_FRAME	0x380
#define EXTRA_CHECK_DEVICE_READY	0
#define USB_HID_KEYREPEAT_USE_SETIDLE	0x0
#define USB_EFIMS_DIRECT_ACCESS	0
#define BOOT_PROTOCOL_SUPPORT	0
#define CLEAR_USB_KB_BUFFER_AT_READYTOBOOT	0
#define SKIP_CARD_READER_CONNECT_BEEP_IF_NO_MEDIA	0
#define PCH_EHCI_OWNERSHIP_CHANGE_MECHANISM	0
#define LEGACY_USB_DISABLE_FOR_USB_MASS	0
#define XHCI_COMPLIANCE_MODE_WORKAROUND	1
#define EFI_USB_HC_INTERRUPT_OUT_SUPPORT	0
#define UINT13_SUPPORT	1
#define USB_I13_DRIVER_VERSION	0x1
#define USBInt1C_SUPPORT	0
#define PEI_OHCI_SUPPORT	0
#define PEI_XHCI_SUPPORT	0
#define PEI_UHCI_IOBASE	0x4000
#define PEI_UHCI_PCI_DEVICES	{0}
#define PEI_OHCI_IOBASE	0xfc087000
#define PEI_XHCI_MMIOBASE	0xfe400000
#define FORCE_RECOVERY	0
#define WHEA_SUPPORT	1
#define DEFAULT_WHEA_NMI_SUPPORT	1
#define FV_WHEA_BLOCKS	0x10
#define FV_WHEA_SIZE	0x10000
#define FV_WHEA_BASE	0xff840000
#define WHEA	1
#define EINJ_BEGIN_INJ_CMD	0x75
#define SMIPORT	0xb2
#define ERST_EXECUTE_OPERATION_CMD	0x70
#define ERST_BUSY_STS_VALUE	0x1
#define ELAR_SIZE	0x2000
#define POLL_INTERVAL	0xea60
#define MAX_ERROR_BLOCK_SIZE	0x2800
#define CSP_SPSUD_SUPPORT	1
#define DISABLE_ME_WORKAROUND	0
#define FPT_START	0x20000
#define FPT_LENGTH	0x10000
#define MFSB_START	0x30000
#define FTPR_START	0x40000
#define FTPR_LENGTH	0x20000
#define MFS_START	0x60000
#define MFS_LENGTH	0x50000
#define OPR1_START	0xb0000
#define OPR2_START	0x1e0000
#define RETRY_OPR_COUNT	0x0
#define CHECK_FPTR_IN_OPR	0
#define RT_OPR_BUFFER	0x400000
#define BITS_OF_SPI_DENSITY	0x1
#define RT32_BINARY_LOCATION	0x2
#define HDD_SECURITY_SUPPORT	1
#define SECURITY_SUPPORT	1
#define MASTER_PASSWORD_ENABLE	1
#define IDE_PASSWORD_LENGTH	0x20
#define DISPLAY_MASTER_PASSWORD	1
#define OEM_DEFAULT_MASTER_PASSWORD	0
#define DEFAULT_MASTER_PASSWORD_REVISION	0xFFFE
#define DISABLED_MASTER_PASSWORD_REVISION	0x1
#define DEFAULT_MASTER_PASSWORD_TAG	amim
#define MASTER_PASSWORD_REVISION_SWITCH	0
#define CHANGED_MASTER_PASSWORD_REVISION	0xFFFE
#define DISABLE_SOFT_SET_PREV	0
#define FORCE_HDD_PASSWORD_PROMPT	0
#define HDD_PASSWORD_ON_NVRAM	0
#define SECUITY_SETUP_ON_SAME_PAGE	0
#define IDE_SECURITY_PLUG_IN	0
#define SW_SMI_HDD_PASSWORD_SAVE	0xd0
#define SW_SMI_HDD_UNLOCK_PASSWORD	0xd1
#define SW_SMI_HDD_PASSWORD_REMOVE	0xd2
#define SW_SMI_HDD_MISC_SMM_FEATURES	0xd3
#define SW_SMI_AHCI_LOCATE_AHCI_SMM	0xd4
#define SETUP_IDE_SECURITY_SUPPORT	1
#define SETUP_ASK_MASTER_PASSWORD	1
#define SETUP_SAME_SYS_HDD_PW	0
#define USER_PASSWORD_RETRY_ATTEMPTS	0x3
#define MAXIMUM_HDD_UNLOCK_ATTEMPTS	0x5
#define ALL_HDD_SAME_PW	0
#define BiosGuard_SUPPORT	1
#define SMM_BIOS_WRITE_PROTECT	1
#define NVRAM_START_SMI_SERVICES_GUID	 { 0xc3e156e4, 0x27b3, 0x4dff, { 0xb8, 0x96, 0xfb, 0x11, 0x3b, 0x2e, 0x68, 0xb5 }}
#define BIOS_GUARD_REG	0x82
#define BIOS_GUARD_CPU_POLICY_OVERRIDE_SUPPORT	1
#define AMI_BIOS_GUARD_SFAM_OEM_1	{0, 0}
#define AMI_BIOS_GUARD_SFAM_OEM_2	{0, 0}
#define AMI_BIOS_GUARD_SFAM_OEM_3	{0, 0}
#define AMI_BIOS_GUARD_SFAM_OEM_4	{0, 0}
#define BIOS_SVN	0x440000
#define BIOS_GUARD_SETUP_SUPPORT	1
#define DEFAULT_BIOS_GUARD_STATE	0
#define BiosGuardMaxSectionSize	0x100000
#define BIOS_GUARD_FLASH_START_ADDRESS	0xff800000
#define FV_NvRamStartingAddress	0x0
#define FV_NvRamLength	0x40000
#define FV_OEM_NCB_StartingAddress	0x40000
#define FV_OEM_NCB_Length	0x10000
#define FV_OAStartingAddress	0x40000
#define FV_OA_Length	0x10000
#define FV_DataStartingAddress	0x6c0000
#define FV_DataLength	0x20000
#define FV_MainStartingAddress	0x50000
#define FV_MainLength	0x670000
#define FV_BBStartingAddress	0x6e0000
#define FV_BBLength	0x120000
#define IS_BIOS_FLASH_SIZE_ALIGNMENT_1MB	0x0
#define INTEL_FIT_SUPPORT	1
#define INTEL_FIT_TABLE_ADDRESS	0xffffffff
#define BIOS_STARTING_ADDRESS	0xff800000
#define FITEntryPointToOtherFVBBRomAddress	0x0
#define BOOT_GUARD_PEI_SUPPORT	0
#define BOOT_GUARD_DXE_SUPPORT	0
#define FIT_HOOK_SUPPORT	1
#define VERIFY_FW_BOOT_GUARD_SUPPORT	0
#define SetupApp_SUPPORT	1
#define SETUPAPP_OUT_FILEFORMAT	1
#define SETUPAPP_USER_FILENAME	PIC%03d.BMP
#define TSE_PRN_SCRN_EVENT_SUPPORT	1
#define TSE_PRN_SCRN_KEY_SCAN	SCAN_F5
#define FIXED_BOOT_ORDER_SUPPORT	0
#define DEFAULT_FIXED_BOOT_ORDER_SUPPORT	0
#define AMIDEBUG_RX_SUPPORT	0
#define S4_WAKE_FROM_RTC_SUPPORTED	1
#define REMOTE_POWER_ON_SUPPORTED	1
#define PROJECT_BUILD_NUMBER_IN_TITLE_SUPPORTED	1
#define DEFAULT_BOOT_TIMEOUT	0x1
#define ON_BOARD_LAN	1
#define SUPPORT_ZERO_BOOT_TIMEOUT	0
#define Setup_SUPPORT	1
#define PASSWORD_MAX_SIZE	0x14
#define PASSWORD_MIN_SIZE	0x3
#define FORCE_USER_TO_SETUP_ON_FIRST_BOOT	0
#define CSP_LIBRARY	1
#define CSP_LIB_MAJOR_VER	0x0
#define CSP_LIB_MINOR_VER	0x11
#define BIOS_TAG	1AQQO014
#define USB_UHCI	0x0
#define USB_EHCI	0x2
#define EHCI_PCI_DEVICES	{0xD0, 0x20}, {0xE8, 0x20}
#define XHCI_PCI_DEVICES	{0xA0, 0x30}
#define UHCI_PCI_DEVICES	{0xD0, 0}, {0xD1, 0}, {0xD2, 0}, {0xD3, 0}, {0xE8, 0}, {0xE9, 0}, {0xEA, 0}, {0xEB, 0}, {0xEC, 0}
#define UHCI_EMUL_PCI_DEVICES	{0xF8, 0x00, 0x01, 0x06, 0x94}
#define USB_CONTROLLERS_WITH_RMH	{0x8086, 0x8C26}, {0x8086, 0x8C2D}
#define PEI_UHCI_SUPPORT	0
#define PEI_EHCI_SUPPORT	1
#define PEI_EHCI_PCI_BDFS	{0x1A0000, 0x1D0000}
#define PEI_EHCI_MEM_BASE_ADDRESSES	{0xFECD0000, 0xfecd0c00}
#define USE_RECOVERY_IMAGE_ON_FLASH_UPDATE	0
#define SMM_CACHE_SUPPORT	1
#define CMOS_USES_STANDARD_BATTERY_TEST	0
#define MAX_MANAGED_CMOS_ADDRESS	0x100
#define SW_IRQ_GENERATION_REG	0x1870
#define DUTY_OFFSET_VAL	0x0
#define DUTY_WIDTH_VAL	0x0
#define RTC_RUNTIME_SERVICES_SUPPORT	1
#define MAX_CAPSULE_BLOCK_DESCRIPTOR_COUNT	0x64
#define CODE_CACHE_SIZE	0x100000
#define TOTAL_FV_BB_SIZE	0x120000
#define FV_BB_SIZE	0x120000
#define CODE_CACHE_PART2_SIZE	0x20000
#define CODE_CACHE_PART2_BASE	0xffee0000
#define ME_IGNITION_FW_MSG_SUPPORT	0
#define CRB_SUPPORT	1
#define CRB_SWSMI	0xbf
#define PROJECT_MAJOR_VERSION	0x0
#define PROJECT_MINOR_VERSION	0xe
#define AMI_SEC_ROM	1AQQO.rom
#define FW_VERSION_GUID	{0x5fe6f6c1, 0x1eac, 0x4ed7, {0x97, 0x42, 0xaf, 0x6c, 0xdd, 0xea, 0xe2, 0xe8}}
#define PCH_SVR_WS_ID_SUPPORT	1
#define DENLOW_SERVER_SUPPORT	1
#define ME_SECOVR_MEI_MSG_SUPPORT	0
#define IntelSaGopDriver_SUPPORT	0
#define SINIT_ACM_SUPPORT	1
#define Recovery_Time_Delay	0x8
#define BOOT_OPTION_TAG_PRIORITIES	BoTagLegacyCdrom, BoTagLegacyHardDisk, BoTagLegacyFloppy, BoTagLegacyEmbedNetwork, BoTagUefi, BoTagEmbeddedShell
#define REFLASH_UPDATE_BOOT_BLOCK	1
#define SUPPORT_WIN8_STYLE_FW_UPDATE	1
#define NO_MMIO_FLASH_ACCESS_DURING_UPDATE	1
#define TRST	0x2
#define BOARD_LABEL_BELOW_25	0
#define S3_BUSY_CLEAR_TIMEOUT	0xfa00
#define POWERON_BUSY_CLEAR_TIMEOUT	0xfa00
#define MAXIMUM_TIMEOUT_FOR_IBFREE	0x1388
#define MATCH_BOOT_OPTION_BY_LOCATION	0
#define SETUP_HIDE_DISABLE_BOOT_OPTIONS	1
#define POPUP_MENU_HIDE_DISABLE_BOOT_OPTIONS	1
#define START_IN_NATIVE_RESOLUTION	0
#define AMI_ROOT_BRIDGE_SUPPORT	0
#define PCI_EXPRESS_GEN2_SUPPORT	0
#define IntelPTT_SUPPORT	0
#define CSP_SPSUD_SUPPORT	1
#define Dptf_SUPPORT	0
#define CSP_MEUD_SUPPORT	1
#define LYNX_POINT_CHIP	0x1
#define MFSB_LENGTH	0x10000
#define OPR1_LENGTH	0x130000
#define OPR2_LENGTH	0x130000
#define RT_ME_BUFFER	0x1000000
#define SETUP_PASSWORD_NON_CASE_SENSITIVE	0
#define EDK_1_05_RETRIEVE_DATA	0
#define IGNORE_IMAGE_ROLLBACK	1
#define FWSIG_SIGNHDR	0x1
#define PRESERVE_SECURE_VARIABLES	1
#define S3_BASE_MEMORY_SIZE	0x100000
#define S3_VIDEO_REPOST_SUPPORT	1
#define ACPI_PM_PROFILE	0x1
#define MPS_TABLE_SUPPORT	1
#define LZMA_SUPPORT	1
#define FAULT_TOLERANT_NVRAM_UPDATE	1
#define NVRAM_RT_GARBAGE_COLLECTION_SUPPORT	1
#define FLASH_SIZE_SELECTION	0x4
#define FLASH_BLOCK_SIZE	0x1000
#define NVRAM_SIZE	0x20000
#define NVRAM_BLOCKS	0x20
#define NVRAM_ADDRESS	0xff800000
#define NVRAM_BACKUP_ADDRESS	0xff820000
#define OEM_NCB_ADDRESS	0xff840000
#define OEM_NCB_SIZE	0x10000
#define OEM_NCB_BLOCKS	0x10
#define FV_DATA_BASE	0xffec0000
#define FV_DATA_SIZE	0x20000
#define OEM_ACTIVATION_TABLE_SIZE	0x10000
#define OEM_ACTIVATION_TABLE_ADDRESS	0xff840000
#define CAR_BASE_ADDRESS	0xff700000
#define SPI_INITIALIZE_WITH_VSCC	1
#define SwitchableGraphics_SUPPORT	0
#define PCH_SKU	0x0
#define CLOCK_GENERATOR_ADDRESS	0xff
#define PMLN	0x100
#define GPLN	0x400
#define PCH_PCIE_ADVANCED_ERROR_REPORTING	1
#define PCH_RCRB_OIC_CEN	0
#define FAST_BOOT_PCI_SKIP_LIST	{{0x01,0xFF},{0x03,0xFF},{0x06,0xFF}}
#define DISABLE_PWR_BUTTON	1
#define x64_BUILD	1
#define SMBIOS_PI_1_1	1
#define CPU_MODULE_CREATE_SMBIOS_TABLES	1
#define SMBIOS_TYPE_4_PROC_UPGRADE	0x24
#define SMBIOS_TYPE_4_MAX_SPEED	0xed8
#define AMI_DEBUGGER_SUPPORT	0
#define SMM_PAGING_MAX_ADDRESS_LINES	0x24
#define DEFAULT_VIDEO_OPROM_POLICY	0x2
#define ENGLISH	en-US
#define ENABLE_RTC_ONE_SECOND_WAKEUP	1
#define CSLIB_WARM_RESET_SUPPORTED	1
#define OEM_ACTIVATION_TABLE_LOCATION	0x1
#define NvramSmiSupport	1
#define CRB_CUSTOM_PPI_SUPPORT	0
#define CRB1_SSID	0x72708086
#define CRB2_SSID	0xeeeeeeee
#define CRB1_SB_PCI_DEVICES_SSID_TABLE	{HECI_BUS_DEV_FUN, CRB1_SSID}, {HECI2_BUS_DEV_FUN, CRB1_SSID}, {IDER_BUS_DEV_FUN, CRB1_SSID}, {KT_BUS_DEV_FUN, CRB1_SSID}, {LAN_BUS_DEV_FUN, CRB1_SSID}, {XHCI_BUS_DEV_FUN, CRB1_SSID}, {EHCI2_BUS_DEV_FUN, CRB1_SSID}, {HDA_BUS_DEV_FUN, CRB1_SSID}, {PCIEBRS_BUS_DEV_FUN, CRB1_SSID}, {PCIEBRS2_BUS_DEV_FUN, CRB1_SSID}, {PCIEBRS3_BUS_DEV_FUN, CRB1_SSID}, {PCIEBRS4_BUS_DEV_FUN, CRB1_SSID}, {PCIEBRS5_BUS_DEV_FUN, CRB1_SSID}, {PCIEBRS6_BUS_DEV_FUN, CRB1_SSID}, {PCIEBRS7_BUS_DEV_FUN, CRB1_SSID}, {PCIEBRS8_BUS_DEV_FUN, CRB1_SSID}, {EHCI_BUS_DEV_FUN, CRB1_SSID}, {PCIBR_BUS_DEV_FUN, CRB1_SSID}, {SB_BUS_DEV_FUN, CRB1_SSID}, {SATA_BUS_DEV_FUN, CRB1_SSID}, {SMBUS_BUS_DEV_FUN, CRB1_SSID}, {SATA2_BUS_DEV_FUN, CRB1_SSID}, {THERMAL_BUS_DEV_FUN, CRB1_SSID}, {-1, -1}
#define CRB1_NB_PCI_DEVICES_SSID_TABLE	{NB_BUS_DEV_FUN, -1}, {NB_IGD_BUS_DEV_FUN, -1}, {NB_PCIEBRNx16_BUS_DEV_FUN, -1}, {NB_PCIEBRNx8_BUS_DEV_FUN, -1}, {NB_PCIEBRNx4_BUS_DEV_FUN, -1}, {-1, -1}
#define CRB2_SB_PCI_DEVICES_SSID_TABLE	{HECI_BUS_DEV_FUN, CRB2_SSID}, {HECI2_BUS_DEV_FUN, CRB2_SSID}, {IDER_BUS_DEV_FUN, CRB2_SSID}, {KT_BUS_DEV_FUN, CRB2_SSID}, {LAN_BUS_DEV_FUN, CRB2_SSID}, {XHCI_BUS_DEV_FUN, CRB2_SSID}, {EHCI2_BUS_DEV_FUN, CRB2_SSID}, {HDA_BUS_DEV_FUN, CRB2_SSID}, {PCIEBRS_BUS_DEV_FUN, CRB2_SSID}, {PCIEBRS2_BUS_DEV_FUN, CRB2_SSID}, {PCIEBRS3_BUS_DEV_FUN, CRB2_SSID}, {PCIEBRS4_BUS_DEV_FUN, CRB2_SSID}, {PCIEBRS5_BUS_DEV_FUN, CRB2_SSID}, {PCIEBRS6_BUS_DEV_FUN, CRB2_SSID}, {PCIEBRS7_BUS_DEV_FUN, CRB2_SSID}, {PCIEBRS8_BUS_DEV_FUN, CRB2_SSID}, {EHCI_BUS_DEV_FUN, CRB2_SSID}, {PCIBR_BUS_DEV_FUN, CRB2_SSID}, {SB_BUS_DEV_FUN, CRB2_SSID}, {SATA_BUS_DEV_FUN, CRB2_SSID}, {SMBUS_BUS_DEV_FUN, CRB2_SSID}, {SATA2_BUS_DEV_FUN, CRB2_SSID}, {THERMAL_BUS_DEV_FUN, CRB2_SSID}, {-1, -1}
#define CRB2_NB_PCI_DEVICES_SSID_TABLE	{NB_BUS_DEV_FUN, CRB2_SSID}, {NB_IGD_BUS_DEV_FUN, CRB2_SSID}, {NB_PCIEBRNx16_BUS_DEV_FUN, CRB2_SSID}, {NB_PCIEBRNx8_BUS_DEV_FUN, CRB2_SSID}, {NB_PCIEBRNx4_BUS_DEV_FUN, CRB2_SSID}, {-1, -1}
#define RP_I210	\_SB.PCI0.RP02
#define SBRX_RP_I210	\_SB.PCI0.RP02.SBRX
#define INTEL_BOOT_GUARD_SUPPORT	0
#define INTEL_BOOT_GUARD_SIGNING_SERVER_SUPPORT	0x0
#define LNKG_TO_EHCI	0x1
#define AMI_INTERRUPT_ROUTE_CONFIG_DEV29_H	PCH_DEV_IR_SETTING( PIRQ_G, PIRQ_D, PIRQ_A, PIRQ_C )
#define AST1300_INIT	0
#define GbtLibrary_SUPPORT	1
#define GbtLib_Library_SUPPORT	1
#define GbtNvram_SUPPORT	1
#define NvramApp_SUPPORT	1
#define GbtCmos_SUPPORT	1
#define GbtDxeLib_SUPPORT	0
#define GbtSmmLib_SUPPORT	0
#define GbtLib_BiosFunc_SUPPORT	1
#define OEM_DATA_SPACE_SIZE	0x3e
#define GbtChassisPost_Support	1
#define GbtOpromScan_SUPPORT	1
#define SLOT_4_ROOT_PORT	0xffffff
#define SLOT_5_ROOT_PORT	0xffffff
#define SLOT_6_ROOT_PORT	0xffffff
#define SLOT_7_ROOT_PORT	0xffffff
#define SLOT_8_ROOT_PORT	0xffffff
#define SLOT_9_ROOT_PORT	0xffffff
#define SLOT_10_ROOT_PORT	0xffffff
#define SLOT_11_ROOT_PORT	0xffffff
#define SLOT_12_ROOT_PORT	0xffffff
#define SLOT_13_ROOT_PORT	0xffffff
#define SLOT_14_ROOT_PORT	0xffffff
#define SLOT_15_ROOT_PORT	0xffffff
#define SLOT_16_ROOT_PORT	0xffffff
#define SLOT_17_ROOT_PORT	0xffffff
#define SLOT_18_ROOT_PORT	0xffffff
#define SLOT_1_CHIP_PORT	0x0
#define SLOT_2_CHIP_PORT	0x0
#define SLOT_3_CHIP_PORT	0x0
#define SLOT_4_CHIP_PORT	0x0
#define SLOT_5_CHIP_PORT	0x0
#define SLOT_6_CHIP_PORT	0x0
#define SLOT_7_CHIP_PORT	0x0
#define SLOT_8_CHIP_PORT	0x0
#define SLOT_9_CHIP_PORT	0x0
#define SLOT_10_CHIP_PORT	0x0
#define SLOT_11_CHIP_PORT	0x0
#define SLOT_12_CHIP_PORT	0x0
#define SLOT_13_CHIP_PORT	0x0
#define SLOT_14_CHIP_PORT	0x0
#define SLOT_15_CHIP_PORT	0x0
#define SLOT_16_CHIP_PORT	0x0
#define SLOT_17_CHIP_PORT	0x0
#define SLOT_18_CHIP_PORT	0x0
#define GBE_LAN_PORT	0x1900
#define LAN_3_ROOT_PORT	0xffffff
#define LAN_3_LANCHIP_PORT	0x0
#define LAN_4_ROOT_PORT	0xffffff
#define LAN_4_LANCHIP_PORT	0x0
#define LAN_5_ROOT_PORT	0xffffff
#define LAN_5_LANCHIP_PORT	0x0
#define LAN_6_ROOT_PORT	0xffffff
#define LAN_6_LANCHIP_PORT	0x0
#define LAN_7_ROOT_PORT	0xffffff
#define LAN_7_LANCHIP_PORT	0x0
#define LAN_8_ROOT_PORT	0xffffff
#define LAN_8_LANCHIP_PORT	0x0
#define LAN_9_ROOT_PORT	0xffffff
#define LAN_9_LANCHIP_PORT	0x0
#define LAN_10_ROOT_PORT	0xffffff
#define LAN_10_LANCHIP_PORT	0x0
#define LAN_11_ROOT_PORT	0xffffff
#define LAN_11_LANCHIP_PORT	0x0
#define LAN_12_ROOT_PORT	0xffffff
#define LAN_12_LANCHIP_PORT	0x0
#define LAN_13_ROOT_PORT	0xffffff
#define LAN_13_LANCHIP_PORT	0x0
#define LAN_14_ROOT_PORT	0xffffff
#define LAN_14_LANCHIP_PORT	0x0
#define LAN_15_ROOT_PORT	0xffffff
#define LAN_15_LANCHIP_PORT	0x0
#define LAN_16_ROOT_PORT	0xffffff
#define LAN_16_LANCHIP_PORT	0x0
#define SLOT1_TYPE	0xff
#define SLOT2_TYPE	0xff
#define SLOT3_TYPE	0xff
#define SLOT4_TYPE	0xff
#define SLOT5_TYPE	0xff
#define SLOT6_TYPE	0xff
#define SLOT7_TYPE	0xff
#define SLOT8_TYPE	0xff
#define SLOT9_TYPE	0xff
#define SLOT10_TYPE	0xff
#define SLOT11_TYPE	0xff
#define SLOT12_TYPE	0xff
#define SLOT13_TYPE	0xff
#define SLOT14_TYPE	0xff
#define SLOT15_TYPE	0xff
#define SLOT16_TYPE	0xff
#define SLOT17_TYPE	0xff
#define SLOT18_TYPE	0xff
#define DEFAULT_SLOT1_OPROM_POLICY	0x1
#define DEFAULT_SLOT2_OPROM_POLICY	0x1
#define DEFAULT_SLOT3_OPROM_POLICY	0x1
#define DEFAULT_SLOT4_OPROM_POLICY	0x1
#define DEFAULT_SLOT5_OPROM_POLICY	0x1
#define DEFAULT_SLOT6_OPROM_POLICY	0x1
#define DEFAULT_SLOT7_OPROM_POLICY	0x1
#define DEFAULT_SLOT8_OPROM_POLICY	0x1
#define DEFAULT_SLOT9_OPROM_POLICY	0x1
#define DEFAULT_SLOT10_OPROM_POLICY	0x1
#define DEFAULT_SLOT11_OPROM_POLICY	0x1
#define DEFAULT_SLOT12_OPROM_POLICY	0x1
#define DEFAULT_SLOT13_OPROM_POLICY	0x1
#define DEFAULT_SLOT14_OPROM_POLICY	0x1
#define DEFAULT_SLOT15_OPROM_POLICY	0x1
#define DEFAULT_SLOT16_OPROM_POLICY	0x1
#define DEFAULT_SLOT17_OPROM_POLICY	0x1
#define DEFAULT_SLOT18_OPROM_POLICY	0x1
#define DEFAULT_LAN1_OPROM_POLICY	0x1
#define DEFAULT_LAN2_OPROM_POLICY	0x1
#define DEFAULT_LAN3_OPROM_POLICY	0x1
#define DEFAULT_LAN4_OPROM_POLICY	0x1
#define DEFAULT_LAN5_OPROM_POLICY	0x1
#define DEFAULT_LAN6_OPROM_POLICY	0x1
#define DEFAULT_LAN7_OPROM_POLICY	0x1
#define DEFAULT_LAN8_OPROM_POLICY	0x1
#define DEFAULT_LAN9_OPROM_POLICY	0x1
#define DEFAULT_LAN10_OPROM_POLICY	0x1
#define DEFAULT_LAN11_OPROM_POLICY	0x1
#define DEFAULT_LAN12_OPROM_POLICY	0x1
#define DEFAULT_LAN13_OPROM_POLICY	0x1
#define DEFAULT_LAN14_OPROM_POLICY	0x1
#define DEFAULT_LAN15_OPROM_POLICY	0x1
#define DEFAULT_LAN16_OPROM_POLICY	0x1
#define DEFAULT_LAN1_Controller_POLICY	0x1
#define DEFAULT_LAN2_Controller_POLICY	0x1
#define DEFAULT_LAN3_Controller_POLICY	0x1
#define DEFAULT_LAN4_Controller_POLICY	0x1
#define DEFAULT_LAN5_Controller_POLICY	0x1
#define DEFAULT_LAN6_Controller_POLICY	0x1
#define DEFAULT_LAN7_Controller_POLICY	0x1
#define DEFAULT_LAN8_Controller_POLICY	0x1
#define DEFAULT_LAN9_Controller_POLICY	0x1
#define DEFAULT_LAN10_Controller_POLICY	0x1
#define DEFAULT_LAN11_Controller_POLICY	0x1
#define DEFAULT_LAN12_Controller_POLICY	0x1
#define DEFAULT_LAN13_Controller_POLICY	0x1
#define DEFAULT_LAN14_Controller_POLICY	0x1
#define DEFAULT_LAN15_Controller_POLICY	0x1
#define DEFAULT_LAN16_Controller_POLICY	0x1
#define AFUWP_SUPPORT	0
#define GbtNmiBtn_SUPPORT	1
#define GbtDxeHooks_Support	1
#define Mac2SMBIOS_SUPPORT	0x1
#define SETUP_ENTRY_SHIFT_STATE	0
#define SETUP_ALT_ENTRY_ENABLE	1
#define SETUP_OEM_KEY1_ENABLE	1
#define SETUP_BBS_POPUP_ENABLE	1
#define SETUP_ENTRY_SCAN	EFI_SCAN_F2
#define SETUP_ENTRY_UNICODE	0x0000
#define POPUP_MENU_ENTRY_SCAN	EFI_SCAN_F10
#define POPUP_MENU_ENTRY_UNICODE	0x0000
#define SETUP_TOGGLE_KEY_SCANCODE	EFI_SCAN_ESC
#define SETUP_TOGGLE_KEY_UNICODE	0x0000
#define SETUP_ALT_ENTRY_SCAN	EFI_SCAN_F2
#define SETUP_ALT_ENTRY_UNICODE	0x0000
#define SETUP_OEM_KEY1_SCAN	SCAN_F12
#define SETUP_OEM_KEY1_UNICODE	0x58
#define SETUP_OEM_KEY1_LEGACY_CODE	0x58
#define SETUP_OEM_KEY1_SHIFT	0x80000000
#define HIDDEN_MENU_KEY_SCANCODE	SCAN_F2
#define HIDDEN_MENU_KEY_SHIFT	(LEFT_CONTROL_PRESSED | LEFT_SHIFT_PRESSED)
#define HIDDEN_PAGE	0xFFFF
#define GbtLanControl_SUPPORT	1
#define GbtLanControlFlog_SUPPORT	1
#define LAN5Gpio	0x29
#define LAN6Gpio	0x3d
#define LAN7Gpio	0x19
#define LAN8Gpio	0x1a
#define LAN9Gpio	0x12
#define LAN10Gpio	0x22
#define GbtIRPower_SUPPORT	0
#define GbtIRPowerPei_SUPPORT	0
#define GbtIRRomHole_SUPPORT	0
#define GbtIRPower2_SUPPORT	0
#define GbtIRPowerPei2_SUPPORT	0
#define GbtIRRomHole2_SUPPORT	0
#define GbtPCI80_Support	1
#define GbtPCI80NvramSet_Support	1
#define GbtPeiSvid_SUPPORT	1
#define GBTPEI_DEBUG	0
#define SBUSLISTEnd	{0xFF,0x00}
#define NBBRLISTEnd	{0xFFFFFFFF}
#define SBBRLISTEnd	{0xFFFFFFFF}
#define SDEVLISTEnd	{0xFFFF,0xFFFF,0xFFFF,0xFFFF}
#define UDEVLISTEnd	{0xFFFF,0xFFFF,0x0}
#define KDEVLISTEnd	{0xFFFF,0xFFFF}
#define SPerrMaskSkipDevList	{-1}
#define GbtCpuOC_Support	0
#define GbtLanLedController_SUPPORT	0
#define GbtLanLedController2_SUPPORT	0
#define GbtLib_PwrFeat_SUPPORT	1
#define GbtAcLossPCH_SUPPORT	1
#define GbtSlpTrap_SUPPORT	1
#define GbtLedBlink_SUPPORT	1
#define GBTPWCapping_SUPPORT	0
#define GbtPwrBtn_SUPPORT	1
#define PwrBtnSensorOff_SUPPORT	1
#define IT8728_GP83_OUT	0
#define IT8732_CONTROL_ACLOSS	0
#define GBT_NOT_PRESENT	0xfc
#define GbtDeepSwich_SUPPORT	0
#define GbtSmiModule_SUPPORT	0
#define GbtLib_Jumper_SUPPORT	1
#define GbtRecovery_SUPPORT	1
#define GBT_SW_RAID_SUPPORT	0
#define GbtLib_Ipmi_SUPPORT	1
#define GbtDxeIpmi_SUPPORT	1
#define BMC_LAN_CHANNEL_NUMBER	{1, 3}
#define GbtFrb3Func_SUPPORT	0
#define OemIpmiInfo_SUPPORT	1
#define DEFAULT_BMC_SDR	0x4a
#define READ_BMC_FRU_VERSION_SUPPORT	1
#define READ_BMC_SDR_VERSION_SUPPORT	1
#define GbtSetCpuSysInfo_SUPPORT	0
#define GbtACLossIPMI_SUPPORT	1
#define GBT_ACLoss_GPIO	0x4
#define GbtAspeedRbu_SUPPORT	0
#define GbtACLossIPMI2_SUPPORT	0
#define GbtLib_HwMonitor_SUPPORT	1
#define GbtFanControl_SUPPORT	0
#define FanCtrlPolicy_SUPPORT	0
#define GbtLib_Include_SUPPORT	1
#define GbtLib_Other_SUPPORT	1
#define ME_CONFIG_SUPPORT	1
#define Denlow_ME_SUPPORT	0
#define DenlowR_ME_SUPPORT	0
#define Romley_ME_SUPPORT	0
#define Cave_ME_SUPPORT	0
#define Broadwell_ME_SUPPORT	1
#define GbtRomHole_SUPPORT	1
#define Gbia_SUPPORT	1
#define FV_GBIA_BASE	0xffe60000
#define GBIA_FILE_PATH	OEMEM\Lib_Gbt\GbtLib_Other\GbtRomHole\GBIA.BIN
#define GbtTseBehavior_SUPPORT	1
#define TSE_USE_AMI_EFI_KEYCODE_PROTOCOL	1
#define SETUP_DELAY_LOGO_TILL_INPUT	0
#define SETUP_PRINT_EVAL_MSG	0
#define CON_OUT_CHECKPOINTS_IN_QUIET_MODE	1
#define POPUP_MENU_SHOW_ALL_BBS_DEVICES	1
#define FULL_VERTICAL_MAIN_DIVIDER	(UINT8)(STYLE_FULL_MAX_COLS*17/24)
#define LanLedPage_SUPPORT	0
#define GBTUSB3_SUPPORT	0
#define OemPciBirfurcation_SUPPORT	0
#define Verbcode_SUPPORT	0
#define GbtTseReplace_SUPPORT	1
#define DELAY_LOGO_ENTER_SETUP	STR_DEL_ENTER_SETUP
#define AspeedGopDriver_SUPPORT	1
#define G200eGopDriver_SUPPORT	0
#define ASPEED_DRIVER_PATH	$(AspeedGopDriver_DIR)\uefi_2300_396_v97.efi
#define LSIScuDriver_SUPPORT	0
#define OemSmbusPei_SUPPORT	0
#define OemSmbusPei2_SUPPORT	0
#define OemPciBirfurcation2_SUPPORT	0
#define IDT_9FGL1214_SetupPage_SUPPORT	0
#define OemClockGenDxe_SUPPORT	0
#define AspeedHwmSetupPage_SUPPORT	0
#define GbtNBBoardVga_Support	0
#define GbtHwm8732_SUPPORT	0
#define GBT9230_SUPPORT	0
#define LAN_Bypass_SUPPORT	0
#define GbtIDEOverride_SUPPORT	0
#define GbtSataDriver_SUPPORT	0
#define GbtLib_Test_SUPPORT	1
#define GbtM105PcieRedriver_SUPPORT	1
#define PCIE_REDRIVER_RETRY_COUNT	0xa
#define GbtMyTseTest_SUPPORT	0
#define GbtLib_GigabitLan_SUPPORT	1
#define Kernel	1
#define IpmiLib_SUPPORT	1
#define GBT_ClearLogoBottom_SUPPORT	0
#define GbtACLossIPMI2_SUPPORT	0
#define Lan_iPXE_OPROM_SUPPORT	0
#define GbtLib_GigabitLan_SUPPORT	1
#define SharedMemory_EC_SetupScreen_SUPPORT	0
#define GbtSmmLib_SUPPORT	0
#define GbtDxeLib_SUPPORT	0
#define GbtSmiModule_SUPPORT	0
#define GbtITEEupSleepSMI_SUPPORT	0
#define GbtITEEupSleep_SUPPORT	0
#define IdeSMART_Support	0
#define HDD_SECURITY_SUPPORT	1
#define PERF_TUNE_SUPPORT	0
#define IT8732_CONFIG_ENV_TABLE	{IT8732_CONFIG_INDEX, 0xFF, 0xFA},{IT8732_CONFIG_DATA,  0xFF, 0x02},
#define GBT9230_SUPPORT	0
#define GbtLoadBMCIP_SUPPORT	1
#define GbtLANMACAddr_SUPPORT	0
#define FIXED_BOOT_ORDER_SUPPORT	0
#define GbtUUIDforBMC_SUPPORT	0x0
#define GBT_BDTEN_READ_DEBUGCODE_TO_CMOS_SUPPORT	0x0
#define LAN_Bypass_SUPPORT	0
#define GbtReadMBID_SUPPORT	0
#define IPMI_DEVICE_SUPPORT	0
#define GbtUsbBoot_SUPPORT	0
#define DEFAULT_Reboot4BmcNotReady	0x1
#define BIOS_TAG_LENGTH	0x9
#define IT8732_CONFIG_GPIO_TABLE	 
#define VERIFY_FW_BOOT_GUARD_SUPPORT	0
#define IR_PROGRAM_PASS_RESET	0
#define SMBIOS_TYPE1_SHOW_IN_MAIN_PAGE	0
#define UNINSTALL_BGRT_TABLE_LEGACY	1
#define GBT_Simple_log_Support	0
#define S4_RESUME_CAN_ENTER_SETUP	0
#define GBT_SW_RAID_SUPPORT	0
#define GbtSataDriver_SUPPORT	0
#define OemActivation_SUPPORT	0
#define Kernel_P	1
#define CPU2_IR	{0x02, 0x60, 0xFFE70000+0x80*1}
#define MEM1_IR	{0x01, 0x64, 0xFFE70000+0x80*2}
#define MEM2_IR	{0x02, 0x64, 0xFFE70000+0x80*3}
#define BMC_SELF_TEST_RETRY	0
#define ACPI_IA_BOOT_ARCH	0x2
#define P0_TXEQB0	0x2933353f
#define P0_TXEQB1	0x2933353f
#define P0_TXEQB2	0x2933353f
#define P0_TXEQB3	0x2933353f
#define P0_TXEQB4	0x2933353f
#define P0_TXEQB5	0x2933353f
#define P0_TXEQB6	0x2933353f
#define P0_TXEQB7	0x2933353f
#define P0_TXEQB8	0x2933353f
#define P0_TXEQB9	0x2933353f
#define P0_CTLEPEAK0	0x44444
#define P0_CTLEPEAK1	0x44444
#define P1_TXEQB0	0x2a32373f
#define P1_TXEQB1	0x2a32373f
#define P1_TXEQB2	0x2a32373f
#define P1_TXEQB3	0x2a32373f
#define P1_TXEQB4	0x2a32373f
#define P1_TXEQB5	0x2a32373f
#define P1_TXEQB6	0x2a32373f
#define P1_TXEQB7	0x2a32373f
#define P1_TXEQB8	0x2a32373f
#define P1_TXEQB9	0x2a32373f
#define P1_CTLEPEAK0	0x0
#define P1_CTLEPEAK1	0x0
#define P2_TXEQB0	0x2930383f
#define P2_TXEQB1	0x2930383f
#define P2_TXEQB2	0x2930383f
#define P2_TXEQB3	0x2930383f
#define P2_TXEQB4	0x2930383f
#define P2_TXEQB5	0x2930383f
#define P2_TXEQB6	0x2930383f
#define P2_TXEQB7	0x2930383f
#define P2_TXEQB8	0x2930383f
#define P2_TXEQB9	0x2930383f
#define P2_CTLEPEAK0	0x0
#define P2_CTLEPEAK1	0x0
#define P3_TXEQB0	0x282f383f
#define P3_TXEQB1	0x282f383f
#define P3_TXEQB2	0x282f383f
#define P3_TXEQB3	0x282f383f
#define P3_TXEQB4	0x282f383f
#define P3_TXEQB5	0x282f383f
#define P3_TXEQB6	0x282f383f
#define P3_TXEQB7	0x282f383f
#define P3_TXEQB8	0x282f383f
#define P3_TXEQB9	0x282f383f
#define P3_CTLEPEAK0	0x66666
#define P3_CTLEPEAK1	0x66666
#define FV_ACM_BASE	0xffed0000
#define FV_FIT_LOCATION	0xffec0000
#define LAN3Gpio	0x2e
#define LAN4Gpio	0xc
#define HIDE_LSI_SAS_2008_DEVICE	0
#define LSI_OPROM_SLOT	0x0
#define GbtSkipWa3615130	0
#define GPIOChange	0xff
#define DEFAULT_PXE_OPROM_POLICY	0x2
#define GbtSataTestMode	0x0
#define GbtSataPort0Length	0x45
#define GbtSataPort1Length	0x45
#define GbtSataPort0Topology	PchDirectConnect
#define GbtSataPort1Topology	PchDirectConnect
#define SATA_SWING_ANDMASK	0x773500
#define SATA_SWING_ORMASK	0x880a00
#define FULLPASEToken	0x3
#define OnboardLan2DID	0x0
#define VirtualIscsiDID	0x5521
#define IntelVID	0x8086
#define INSTALL_KEYBOARD_MOUSE_ALWAYS	0
#define GbtEfiBootOptionPolicy	0x0
#define DEFAULT_MASS_STORAGE_OPROM_POLICY	0x2
#define GbtPERRSensor	0x0
#define GbtSERRSensor	0x0
#define GbtPERR_token	0x4
#define GbtSERR_token	0x5
#define ERR2_Token	0x6
#define ROOTCONToken	0x6
#define DEVCNTToken	0x6
#define RPEDMASKToken	0x1
#define RPERRCMDToken	0x6
#define QPI_P_ERRMSK_Token	0x4404
#define BIOS_SECURITY	0
#define OemSmbusPei2_CaveCreek_InitRedriverAtBootTime	0
#define GbtMemory_ECC_LED_Support	0
#define GbtATRToken	0xc00000
#define CPU0_Dev1_Gen2	0x6600
#define CPU1_Dev1_Gen2	0x6600
#define CPU0_Dev1CTLE	0x6622
#define CPU1_Dev1CTLE	0x6622
#define CPU0_Dev3CTLE	{0xAAAA6666,0x6666AAAA}
#define CPU1_Dev3CTLE	{0xAAAA6666,0x6666AAAA}
#define CPU0_Dev3_Gen2	{0x66666666,0x66666666}
#define CPU1_Dev3_Gen2	{0x66666666,0x66666666}
#define FWCAPSULE_FILE_FORMAT	0
#define LOCK_PPM_CSR	0
#define OC_LOCK_ENABLE	0
#define SHELL_TEXT_MODE	0x0
#define GbtChgVDDGPIO	0
#define CLASSIFY_ERROR	0
#define QUIET_BOOT_MESSAGE_	Press <F2> to enter setup, <F10> Display Boot Menu, <F12> to enter PXE Boot
#define QUIET_BOOT_MESSAGE()	CONVERT_TO_WSTRING(QUIET_BOOT_MESSAGE_)
#define ENTER_SETUP_MESSAGE_	Entering Setup...
#define ENTER_SETUP_MESSAGE()	CONVERT_TO_WSTRING(ENTER_SETUP_MESSAGE_)
#define BOOT_GUARD_ACM	0x1
#define GbtPowerOnRtc74h_SUPPORT	0
#define Lan1PresentGPIOPin	0xFFFFFF
#define Lan2PresentGPIOPin	0xFFFFFF
#define Lan3PresentGPIOPin	0xFFFFFF
#define Lan4PresentGPIOPin	0xFFFFFF
#define Lan5PresentGPIOPin	0xFFFFFF
#define Lan6PresentGPIOPin	0xFFFFFF
#define Lan7PresentGPIOPin	0xFFFFFF
#define Lan8PresentGPIOPin	0xFFFFFF
#define GP28_S4S5_V	0x0
#define GP28_WAK_V	0x1
#define ROOT_PORT_FUN_SWAP_ENABLE	0
#define LEGACY_TO_EFI_BOOT_SUPPORT	0
#define PCI_DEVICE_64BIT_RESOURCE_THRESHOLD	0x1000000000
#define FULL_STYLE_CONTROL_MAIN_PAGE_MARGIN	FULL_STYLE_CONTROL_LEFT_MARGIN
#define PROCESSOR_CHARACTERISTICS	0x0004
#define AMI_SILENT_BOOT_LOAD_DEFAULT	0
#define NONE	0xffffff
#define SEL_LOG_TYPE_SUPPORT	0x0
#define ECC_LOG_TO_DMI_SUPPORT	1
#define ECC_SMI_DISABLE_SUPPORT	0
#define QUIET_BOOT_SHOW_LOG_ENTER_OS	0
#define TYPE15_REMOVE_SUPPORT	0
#define IpmiBootDoNotClearBootFlagValidBit_SUPPORT	0
#define CANCEL_ESCKEY_IN_BOOTDEVICEMENU_ENABLE	0
#define UEFI_LAN_DEVICE_APPEND_MAC	0
#define LAN_UEFI_DRIVER_DEPENDEX	0
#define BIOS_LOCK_ENABLE	0
#define SATA_PORT1_LENGTH_CONFIG	{0, 0, 0, 0, 0, 7}
#define SATA_PORT2_LENGTH_CONFIG	{0, 0, 0, 0, 0, 7}
#define SATA_PORT3_LENGTH_CONFIG	{0, 0, 0, 0, 0, 7}
#define SATA_PORT4_LENGTH_CONFIG	{0, 0, 0, 0, 0, 7}
#define SATA_PORT5_LENGTH_CONFIG	{0, 0, 0, 0, 0, 7}
#define SATA_PORT6_LENGTH_CONFIG	{0, 0, 0, 0, 0, 7}
#define PROJECT_TAG	1AQQO
#define Kernel_GPIO	1
#define GbtOemFunc_SUPPORT	1
#define MAC_STRING_TOKEN	%02X-%02X-%02X-%02X-%02X-%02X
#define LAN1_OFFSET	Lan1Controller
#define LAN2_OFFSET	Lan2Controller
#define LAN3_OFFSET	Lan3Controller
#define LAN4_OFFSET	Lan4Controller
#define LAN5_OFFSET	Lan5Controller
#define LAN6_OFFSET	Lan6Controller
#define LAN7_OFFSET	Lan7Controller
#define LAN8_OFFSET	Lan8Controller
#define DEFAULT_ChassisMode	0x0
#define GbtOemServerSetup_SUPPORT	1
#define Kernel_D_D	1
#define Kernel_R_D	0
#define Kernel_P	1
#define OEM_BIOS_VERSION	R09
#define GBTMRCVer	2.5.0.0
#define GBTMeSPI	SPS_EN_03.00.07.024.0_PV-D-R-BDW_LPT_REL
#define Gbt_Chipset	2
#define Gbt_Refresh	2
#define Select_Logo	1
#define DEBUG_MODE	0
#define MRC_DEBUG_MESSAGE	0
#define MRC_DEBUG_PRINT_SUPPORT	0
#define MICROCODE_SPLIT_BB_UPDATE	1
#define SERIAL_STATUS_SUPPORT	1
#define COM0_DEFAULT_CONSOLE_REDIRECTION_ENABLE	0
#define AMIDEBUG_RX_SUPPORT	0
#define USB_XHCI	0x2
#define XHCI_EVENT_SERVICE_MODE	0x0
#define USB_DEV_HUB_COUNT	0x9
#define USB_OVER_CURRENT_MAPPING_SETTINGS	1, 1, 0, 0, 8, 8, 8, 8, 2, 2, 8, 8, 8, 8
#define USB30_OVER_CURRENT_MAPPING_SETTINGS	0, 0, 8, 8, 8, 8
#define USB_PORTS_LENGTH	0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80
#define USB_PORT_LOCATION_CONFIG	7, 7, 7, 7, 1, 1, 1, 1, 7, 7, 7, 7, 1, 1
#define NUMBER_OF_SLOT	0x1
#define SLOT_1_ROOT_PORT	0x100
#define SLOT_2_ROOT_PORT	0xffffff
#define SLOT_3_ROOT_PORT	0xffffff
#define NUMBER_OF_ONBOARD_LAN	0x2
#define LAN_1_ROOT_PORT	0x1c00
#define LAN_1_LANCHIP_PORT	0x0
#define LAN_2_ROOT_PORT	0x1c01
#define LAN_2_LANCHIP_PORT	0x0
#define PasswordClrPin	0x6
#define IT8728_CIR_PORT_PRESENT	0
#define IT8728_FLOPPY_PORT_PRESENT	0
#define IT8728_PARALLEL_PORT_PRESENT	0
#define IT8728_HWM_SUPPORT	1
#define IT8728_SMBUS_SUPPORT	1
#define IT8732_PARALLEL_PORT_PRESENT	0
#define IT8732_KEYBOARD_PRESENT	0
#define IT8732_MOUSE_PRESENT	0
#define IT8732_CIR_PORT_PRESENT	0
#define IT8732_HWM_PRESENT	0
#define EXT_SMB_SENSOR_EN	0
#define PECI_SEL	0x0
#define PECI2_EN	0
#define PECI_HOST_SEL	0x0
#define TEMP3_THERMAL_RES	1
#define TEMP3_THERMAL_DOIDE	0
#define TEMP2_THERMAL_RES	1
#define TEMP2_THERMAL_DOIDE	0
#define TEMP1_THERMAL_RES	1
#define TEMP1_THERMAL_DOIDE	0
#define IT8732_ECFW_SUPPORT	0
#define IT8732_ONOFFMODE_SUPPORT	0
#define RESERVED_PAGE_ROUTE	0
#define CSM_DEFAULT_VMODE_SWITCHING	0x1
#define IR_ROM_ADDRESS	0xffe70000
#define IR_ROM_FILE_PATH	OEMEM\6LISL\Oprom\IRROM.BIN
#define IR_DATASIZE	0x80
#define SWITCH_ADDRESS	0xe4
#define NUMBER_OF_IR	0x1
#define CPU1_IR	{0xFF, 0x60, 0xFFE70000+0x80*0}
#define IR_LIST	{0xFF, 0x60, 0xFFE70000+0x80*0}
#define SLP_STRING	GIGABYTE_WSS
#define GO20	0x0
#define GO9	0x0
#define GO21	0x0
#define GO27	0x0
#define GO28	0x1
#define BMC_LAN1_CHANNEL_NUMBER	0x1
#define BMC_LAN2_CHANNEL_NUMBER	0x3
#define BMC_LAN_COUNT	0x1
#define GBT_NMI_BTN_GPIO	0xb
#define CPU_60W	{0x32, 0x42, 0x7A, 0xC0, 0x43, 0x32, 0x42, 0x7A, 0xC0, 0x43, 0x32, 0x42, 0x7A, 0xC0, 0x43}
#define CPU_70W	{0x32, 0x42, 0x7A, 0xC0, 0x43, 0x32, 0x42, 0x7A, 0xC0, 0x43, 0x32, 0x42, 0x7A, 0xC0, 0x43}
#define CPU_80W	{0x32, 0x50, 0x7A, 0xA2, 0x43, 0x32, 0x50, 0x7A, 0xA2, 0x43, 0x32, 0x50, 0x7A, 0xA2, 0x43}
#define CPU_95W	{0x32, 0x50, 0x7A, 0xA2, 0x43, 0x32, 0x50, 0x7A, 0xA2, 0x43, 0x32, 0x50, 0x7A, 0xA2, 0x43}
#define CPU_115W	{0x32, 0x5C, 0x7A, 0x9A, 0x43, 0x32, 0x5C, 0x7A, 0x9A, 0x43, 0x32, 0x5C, 0x7A, 0x9A, 0x43}
#define CPU_130W	{0x32, 0x5C, 0x7A, 0x9A, 0x43, 0x32, 0x5C, 0x7A, 0x9A, 0x43, 0x32, 0x5C, 0x7A, 0x9A, 0x43}
#define CPU_135W	{0x32, 0x52, 0x7A, 0xA0, 0x43, 0x32, 0x52, 0x7A, 0xA0, 0x43, 0x32, 0x52, 0x7A, 0xA0, 0x43}
#define CPU_150W	{0x32, 0x5C, 0x7A, 0x9A, 0x43, 0x32, 0x5C, 0x7A, 0x9A, 0x43, 0x32, 0x5C, 0x7A, 0x9A, 0x43}
#define PowerButtonLockPin	0x3d
#define SmbusSwitchPin	0x11
#define ROMLEY_PLATFORM_TYPE	0x1
#define AMI_ROM	flashabl.ROM
#define FWCAPSULE_FILE_NAME	flashabl.CAP
#define FLASH_SIZE	0x800000
#define IT8728_CLOCK	0x0
#define IT8732_CLOCK	0x0
#define TOTAL_SIO_SERIAL_PORTS	0x2
#define TOTAL_PCI_SERIAL_PORTS	0x0
#define DEFAULT_ACPI_SPCR_CONSOLE_REDIRECTION_ENABLE	0
#define NCT6681D_SUPPORT	0
#define NCT6681D_SERIAL_PORT0_PRESENT	0
#define NCT6681D_SERIAL_PORT1_PRESENT	0
#define NCT6681D_FLOPPY_PORT_PRESENT	0
#define NCT6681D_PARALLEL_PORT_PRESENT	0
#define NCT6681D_KEYBOARD_PRESENT	0
#define NCT6681D_VID_PRESENT	0
#define NCT6681D_ENV_CONTROLLER_PRESENT	0
#define NCT6681D_ACPI_PRESENT	0
#define NCT6681D_CIR_PORT_PRESENT	0
#define CRB_SIO_SUPPORT	0
#define A_S1	0
#define OFBD_VERSION	0x210
#define PAUSEKEY_SUPPORT	1
#define T_ACPI_OEM_ID	GBTSYS
#define T_ACPI_OEM_TBL_ID	GBTPRDCT
#define RecoveryPin	0x46
#define OEM_SVID	0x1458
#define OEM_SSID	0xffff
#define SKIP_EARLY_BCV_DEVICES	{0x3f20105a, 0x3781105a}
#define PROGRAM_AST2300_VGA_SSVID	1
#define OnBoardVgaBridgePFA	0x1c02
#define RETRY_COUNT	0x2
#define TSE_MULTILINE_CONTROLS	1
#define OEM_PROMOTE_BMC_VIRTUAL_DEVICE	0x1
#define ALWAYS_PUBLISH_HII_RESOURCES	1
#define IODECODETYPE	1
#define Hide_Boot_item	1
#define DEFAULT_QUIET_BOOT	1
#define DEFAULT_YEAR	0x7dc
#define Gbt_PartNumconcatenate	0
#define Type4Voltage	0x36b0
#define GbtType16Capacity	0x6000000
#define Gbt_Type19_Partition	0x1
#define USBOCM1_AND	0
#define USBOCM2_AND	0
#define USBOCM1_OR	0xC0300C03
#define USBOCM2_OR	0
#define Gbt_DisablePci2PciBridge	0
#define Gbt_FAST_BOOT	0x0
#define Gbt_CKE_Mode	0x0
#define Gbt_MEM_PWR_SAV	0x0
#define DEBUG_COM_PORT_ADDR	0x3f8
#define HTRE	0x0
#define PGbtCI_Bridge_Support	0
#define GbtUSBIRA_Token	0x371b
#define G_Type4_L1CacheConfig	0x180
#define G_Type4_L2CacheConfig	0x181
#define G_Type4_L3CacheConfig	0x182
#define Type7SSRAM	0x58
#define Type7CSRAM	0x40
#define ERRORCacheLevel	0x5
#define G_Type4_Voltage	0x80
#define PS2E	0x0F
#define BMNN	0x62
#define BMAX	0x62
#define BMLL	0x2
#define B2NN	0x65
#define B2AX	0x65
#define B2LL	0xb
#define B3NN	0x67
#define B3AX	0x67
#define B3LL	0x9
#define SetTimeStampFunc	1
#define POST_ERR_CODE	1
#define GbtMemErrCorrection	0x5
#define CreateID	0x0
#define Gbt_DontUseCrbLibToUpdateSvid	0x1
#define MAX_DIMM_DPC	0x2
#define LAN1Gpio	0x2c
#define LAN2Gpio	0xe
#define ONBOARD_VIDEO_ROOT_PORT_BUS_NUM	0x0
#define ONBOARD_VIDEO_ROOT_PORT_DEV_NUM	0x1c
#define ONBOARD_VIDEO_ROOT_PORT_FUN_NUM	0x3
#define DISABLE_CA_ERROR_ON_PATSBURG_ROOTPORT_VIDEO_DEVICE	1
#define FACP_FLAG_SLP_BUTTON	1
#define INT10_TRUST_EDID_INFORMATION	0
#define PMM_EBDA_LOMEM_SIZE	0x60000
#define PMM_LOMEM_SIZE	0x30000
#define PMM_HIMEM_SIZE	0x9600000
#define SAS_ROOT_PORT	0xffffff
#define FV_BB_BLOCKS	0x120
#define FV_BB_BASE	0xffee0000
#define FV_MAIN_BASE	0xff850000
#define FV_MAIN_BLOCKS	0x670
#define DETECT_PS2_KEYBOARD	0
#define DETECT_PS2_MOUSE	0
#define CRB_HDA_VERB_TABLE_PRESENT	0
#define DEFAULT_SECURE_BOOT_ENABLE	0
#define OEM_USBPREPORT_DISABLE_SUPPORT	1
#define TSE_ROMHOLE_SUPPORT	1
#define ROMHOLE_NUMBER_OF_BLOCK	0x25
#define XHCI_SUPPORT	1
#define INTERRUPTS_TO_PRESERVE	{0x13, 0x40, 0x08}
#define LVC_BOARD	0x1
#define CONOUT_CHECKPOINTS_SUPPORT	1
#define EXTENDED_RESOLUTION_ENABLE	1
#define PCIE_REDRIVER_VALUE	{0x06,0x18},{0x0f,0x01},{0x10,0xa8},{0x11,0x82},{0x16,0x01},{0x17,0xa8},{0x18,0x82},{0x1d,0x01},{0x1e,0xa8},{0x1f,0x82},{0x24,0x01},{0x25,0xa8},{0x26,0x82},{0x2c,0x00},{0x2d,0xa8},{0x2e,0x82},{0x33,0x00},{0x34,0xa8},{0x35,0x82},{0x3a,0x00},{0x3b,0xa8},{0x3c,0x82},{0x41,0x00},{0x42,0xa8},{0x43,0x82}
#define SSP1_UPC	0xFF,0x03,0x00,0x00
#define SSP1_PLD	0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00
#define SSP1_PR3	0x1
#define SSP2_UPC	0xFF,0x03,0x00,0x00
#define SSP2_PLD	0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00
#define SSP2_PR3	0x2
#define SSP3_UPC	0x00,0x00,0x00,0x00
#define SSP3_PLD	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
#define SSP3_PR3	0x4
#define SSP4_UPC	0x00,0x00,0x00,0x00
#define SSP4_PLD	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
#define SSP4_PR3	0x8
#define SSP5_UPC	0x00,0x00,0x00,0x00
#define SSP5_PLD	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
#define SSP5_PR3	0x10
#define SSP6_UPC	0x00,0x00,0x00,0x00
#define SSP6_PLD	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
#define SSP6_PR3	0x20
#define SETUP_HIDE_BIOS_SIGNON_MESSAGE2	1
#define GC_MODE0	{ 0, 80, 25, 0, 0 }
#define PCIEX_BASE_ADDRESS	0xe0000000
#define ABOVE_4G_PCI_DECODE	1
#define AUTO_ENABLE_ABOVE_4G_PCI_DECODE_IN_OUT_OF_RESOURCES	1
#define Kernel_D	1
#define Kernel_GPIO	1
#define GPIO_000	0x3
#define GPIO_001	0x3
#define GPIO_002	0x0
#define GPIO_003	0x0
#define GPIO_004	0x0
#define GPIO_005	0x0
#define GPIO_006	0xb
#define GPIO_007	0x3
#define GPIO_008	0x5
#define GPIO_009	0x0
#define GPIO_010	0x5
#define GPIO_011	0xb
#define GPIO_012	0x3
#define GPIO_013	0x3
#define GPIO_014	0x5
#define GPIO_015	0x3
#define GPIO_016	0x3
#define GPIO_017	0x5
#define GPIO_018	0x0
#define GPIO_019	0x3
#define GPIO_020	0x5
#define GPIO_021	0x3
#define GPIO_022	0x0
#define GPIO_023	0x3
#define GPIO_024	0x0
#define GPIO_025	0x3
#define GPIO_026	0x5
#define GPIO_027	0x0
#define GPIO_028	0x5
#define GPIO_029	0x0
#define GPIO_030	0x3
#define GPIO_031	0x3
#define GPIO_032	0x1
#define GPIO_033	0x3
#define GPIO_034	0x3
#define GPIO_035	0x0
#define GPIO_036	0x0
#define GPIO_037	0x0
#define GPIO_038	0x0
#define GPIO_039	0x0
#define GPIO_040	0x0
#define GPIO_041	0x0
#define GPIO_042	0x5
#define GPIO_043	0x5
#define GPIO_044	0x5
#define GPIO_045	0x5
#define GPIO_046	0x1
#define GPIO_047	0x0
#define GPIO_048	0x0
#define GPIO_049	0x0
#define GPIO_050	0x3
#define GPIO_051	0x3
#define GPIO_052	0x3
#define GPIO_053	0x3
#define GPIO_054	0x3
#define GPIO_055	0x3
#define GPIO_056	0x0
#define GPIO_057	0x0
#define GPIO_058	0x0
#define GPIO_059	0x0
#define GPIO_060	0x3
#define GPIO_061	0x1
#define GPIO_062	0x5
#define GPIO_063	0x0
#define GPIO_064	0x3
#define GPIO_065	0x3
#define GPIO_066	0x3
#define GPIO_067	0x0
#define GPIO_068	0x3
#define GPIO_069	0x3
#define GPIO_070	0x3
#define GPIO_071	0x3
#define GPIO_072	0x5
#define GPIO_073	0x5
#define GPIO_074	0x3
#define GPIO_075	0x0
#define Kernel	1
#define Kernel_smbios	0x0
#define AspeedGopDriver_SUPPORT	1
#define DCMI_SUPPORT	0
#define IPMI_SUPPORT	1
#define GbtIRPower_SUPPORT	0
#define GbtIRPowerPei_SUPPORT	0
#define PILOT3_SIO_SUPPORT	0
#define IT8728_SUPPORT	0
#define IT8732_SUPPORT	0
#define GbtSOL_OVERWRITE	1
#define GbtSlp10_SUPPORT	1
#define GbtGbiaHole_SUPPORT	1
#define GbtAcLossPCH_SUPPORT	1
#define GbtACLossIPMI_SUPPORT	1
#define GbtChassisErrPause_SUPPORT	1
#define GbtLoadDefault_SUPPORT	1
#define GBT_BmcSelFull_SUPPORT	1
#define AST2300_SUPPORT	1
#define GbtOpromScan_SUPPORT	1
#define AFUWP_SUPPORT	0
#define OEM_PASSWORD_CLEARN_SUPPORT	1
#define GbtEventLog_SUPPORT	1
#define GbtSlpTrap_SUPPORT	1
#define GbtPowerOnPme_SUPPORT	1
#define GbtPowerOnRing_SUPPORT	1
#define GbtPowerOnRtc_SUPPORT	1
#define GbtFrb3Func_SUPPORT	0
#define GBTPOSTCODETOBMC	0
#define GbtLedBlink_SUPPORT	1
#define GbtBmcLanCfg_SUPPORT	1
#define ME_CONFIG_SUPPORT	1
#define GbtNmiBtn_SUPPORT	1
#define GbtFanControl_SUPPORT	0
#define NvidiaSLI_SUPPORT	0
#define GbtPowerButtonLock_SUPPORT	0
#define GbtSmbusSwitch_SUPPORT	1
#define SEND_IPMI_SMBIOS_SUPPORT	0
#define EmptyLogo_SUPPORT	0
#define EnforceSetupGbt	1
#define GbtUUID_SUPPORT	0
#define GbtRecovery_SUPPORT	1
#define GbtPeiSvid_SUPPORT	1
#define GbtLanFailoverMode_SUPPORT	0
#define CryptoAPI_SUPPORT	1
#define WIN8_FEATURE_SUPPORT	1
#define SecureMod_SUPPORT	1
#define SmiVariable_SUPPORT	1
#define WORKSHOP_SUPPORT	1
#define VoltageDIMM_SUPPORT	1
#define FruSetupScreen_SUPPORT	1
#define OemIpmiInfo_SUPPORT	1
#define LanLedPage_SUPPORT	0
#define ErrorLogging_SUPPORT	0
#define GBTUSB3_SUPPORT	0
#define OemPciBirfurcation_SUPPORT	0
#define Verbcode_SUPPORT	0
#define LSIScuDriver_SUPPORT	0
#define GbtLanControl_SUPPORT	1
#define LanSwitchGPIO	1
#define OemSmbusPei_SUPPORT	0
#define OemSmbusPei2_SUPPORT	0
#define GbtGetFCBVersion_SUPPORT	0
#define GbtMAC2BMC_SUPPORT	0
#define FixedFRB3LogTooMuch_SUPPORT	0
#define GbtIRPower2_SUPPORT	0
#define GbtSetCpuSysInfo_SUPPORT	0
#define GBTPWCapping_SUPPORT	0
#define GbtPCI80_Support	1
#define GbtPCI80NvramSet_Support	1
#define SecFlashUpd_SUPPORT	1
#define OemPciBirfurcation2_SUPPORT	0
#define GbtCpuOC_Support	0
#define LPT_DEBUG	0x0
#define SataDriver_SUPPORT	1
#define AST1300_INIT	0
#define FanCtrlPolicy_SUPPORT	0
#define GbtHwm8732_SUPPORT	0
#define GbtNBBoardVga_Support	0
#define GbtAspeedRbu_SUPPORT	0
#define GbtM105PcieRedriver_SUPPORT	1
#define GbtGetBMCLanMAC_SUPPORT	1
#define GbtOpenRack_SUPPORT	0
#define Gbt_BMCRedriver_Support	1
#define BoardPciRes_SUPPORT	1
#define PCI_OUT_OF_RESOURCE_SETUP_SUPPORT	1
#define NetBootHotKey_SUPPORT	1
#define GbtSetupScreen_SUPPORT	1
#define SHOW_MAIN_FORMSET	1
#define SHOW_ADVANCED_FORMSET	1
#define SHOW_CHIPSET_FORMSET	1
#define SHOW_SECURITY_FORMSET	1
#define SHOW_BOOT_FORMSET	1
#define SHOW_EXIT_FORMSET	1
#define GbtVfr_SUPPORT	1
#define GbtPowerPolicy_SUPPORT	0
#define EXTRA_RESERVED_BYTES	0x1000
#define SYSTEM_PRODUCT_NAME	GA-6LISL(C226)
#define SYSTEM_SKU_NUMBER	\x20\x20\x20\x20\x20\x20\x20\x20
#define SYSTEM_FAMILY	Server
#define SMBIOS_UUID	{0,2,0,3,0,4,0,5,0,6,0,7,0,8,0,9}
#define BASE_BOARD_INFO	1
#define NUMBER_OF_BASEBOARDS	0x1
#define NUMBER_OF_OBJECT_HANDLES	0x0
#define SYS_CHASSIS_INFO	1
#define ELEMENT_COUNT	0x0
#define ELEMENT_LEN	0x0
#define NO_OF_PROCESSOR_SOCKETS	0x1
#define MEM_CTRL_INFO	0
#define MEM_MODULE_INFO	0
#define EXTERNAL_CACHE_INFORMATION	0
#define PORT_CONNECTOR_INFO	0
#define NUMBER_OF_SYSTEM_SLOTS	0x3
#define ONBOARD_DEVICE_INFO	0
#define NUMBER_OF_ONBOARD_DEVICES	0x1
#define OEM_STRING_INFO	1
#define NUMBER_OF_OEM_STRINGS	0x1
#define SYSTEM_CONFIG_OPTION_INFO	1
#define NUMBER_OF_SYSTEM_CONFIG_STRINGS	0x1
#define BIOS_LANGUAGE_INFO	1
#define BIOS_LANGUAGE_FORMAT	0
#define FLASH_MEMORY_ARRAY_INFO	0
#define NO_OF_PHYSICAL_MEMORY_ARRAY	0x1
#define A1_MEMORY_SOCKETS	0x2
#define MEMORY_ERROR_INFO	0
#define MEMORY_DEVICE_INFO	1
#define BUILTIN_POINTING_DEVICE_INFO	0
#define PORTABLE_BATTERY_INFO	0
#define NO_OF_PORTABLE_BATTERY	0x4
#define SYSTEM_RESET_INFO	0
#define HARDWARE_SECURITY_INFO	0
#define SYSTEM_POWER_CONTROLS_INFO	0
#define VOLTAGE_PROBE_INFO	0
#define COOLING_DEVICE_INFO	0
#define TEMPERATURE_PROBE_INFO	0
#define ELECTRICAL_PROBE_INFO	0
#define OUT_OF_BAND_REMOTE_ACCESS_INFO	0
#define BIS_INFO	0
#define SIXTY_FOURBIT_MEMORY_ERROR_INFO	0
#define MANAGEMENT_DEVICE_INFO	0
#define MEMORY_CHANNEL_INFO	0
#define NUMBER_OF_MEMORY_CHANNELS	0x1
#define IPMI_DEVICE_INFO	0
#define SYSTEM_POWER_SUPPLY_INFO	0
#define NUMBER_OF_POWER_SUPPLY	0x1
#define ADDITIONAL_INFO	0
#define ADDITIONAL_INFO_COUNT	0x3
#define ONBOARD_DEVICE_EXTENDED_INFO	0
#define ONBOARD_DEVICE_EXT_COUNT	0x3
#define INTEL_ASF	0

#endif

//-------- DO NOT EDIT THIS FILE --------
//
// FILE WAS GENERATED AUTOMATICALY USING AMISDL v3.64.1065 Test Only (Mar 15 2013,03:42:45)
//
//-------- DO NOT EDIT THIS FILE --------
//****************************************************************************
//****************************************************************************
//**                                                                        **
//**         (C)Copyright 1985-2013, American Megatrends, Inc.              **
//**                                                                        **
//**                          All Rights Reserved.                          **
//**                                                                        **
//**         5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
//**                                                                        **
//**                          Phone (770)-246-8600                          **
//**                                                                        **
//****************************************************************************
//****************************************************************************
//****************************************************************************
