• PCChips/Hsin Tech TX Pro II
• PCChips/Hsin Tech Super TX3

The SiS 5598 is a highly integrated single-chip chipset solution developed by Silicon Integrated Systems for Pentium-based PCI/ISA systems. The physical layout of the chip was specifically optimized for motherboards using the ATX and Baby-AT form factors. A notable characteristic of the chipset is its integrated 64-bit graphics and video accelerator, which utilizes a shared memory architecture with the system's main DRAM. The integration of graphics and core logic functions onto a single chip was intended to reduce overall system cost and board complexity.

Core System Architecture

• CPU Support: The chipset supports Intel Pentium processors, including variants with MMX technology, and other compatible CPUs. It accommodates host bus frequencies of 50, 55, 60, 66, and 75 MHz.
• Memory Controller: An integrated DRAM controller supports a maximum of 384MB of main memory distributed across three banks. The controller is compatible with Fast Page Mode (FPM), Extended Data Out (EDO), and Synchronous DRAM (SDRAM) modules. It interfaces with a full 64-bit processor data bus.
• L2 Cache: An integrated second-level (L2) cache controller is included, supporting cache sizes of 256KB and 512KB. The cache operates in a direct-mapped, write-back configuration.

Integrated Components

The SiS 5598 consolidates numerous system functions into a single BGA package. These integrated functions include:

• A Host-to-PCI bridge and a PCI-to-ISA bridge.
• A 64-bit 2D graphics and video accelerator.
• A PCI Bus Master IDE controller with support for PIO modes 0-4, Multiword DMA modes 0-2, and Ultra DMA/33.
• A Universal Serial Bus (USB) host controller with two ports, compliant with the OpenHCI specification.
• An integrated Keyboard Controller with support for a PS/2 mouse interface.
• An integrated Real Time Clock (RTC) with 256 bytes of CMOS SRAM.
• A power management unit compliant with the Advanced Configuration and Power Interface (ACPI) specification.

Graphics Subsystem

The integrated graphics controller is a 32-bit PCI device that features an enhanced 64-bit BitBLT graphics engine. It employs a Unified Memory Architecture (UMA) by sharing a configurable portion of the main system memory, ranging from 0.5MB to 4MB, for its frame buffer. This design obviated the need for a dedicated graphics card and associated video memory. The subsystem also incorporates a programmable 24-bit true-color RAMDAC and a dual-clock generator.

Technical Specifications

• PCI Bus: Fully compliant with the PCI specification revision 2.1 and includes an arbiter for up to 4 PCI masters.
• Package: 553-ball Ball Grid Array (BGA).
• Process Technology: Fabricated using a 0.35µm, 3.3V CMOS process.