Loongson LS3A5000
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See all boards with this chip| Specifications | |
|---|---|
| Cache | Each processor core contains a 64KB private level-1 instruction cache and 64KB private level-1 data cache; Each processor core contains 256KB of private second-level cache; All processor cores share a 16MB level 3 cache |
| Frequency | 2.3GHz-2.5GHz |
| Other I/O | 1 SPI, 1 UART, 2 I2C, 16 GPIO interfaces |
| High-speed I/O | 2 HyperTransport 3.0 controllers; supports Multiprocessor Data Consistency Interconnect (CC-NUMA) |
| Number of cores | 4 |
| Processor cores | Support LoongArch® command system; Support 128/256-bit vector instructions; Four launches are executed out of order; 4 fixed-point elements, 2 vector elements and 2 memory access units |
| Memory interface | 2 x 72-bit DDR4-3200 controllers; Support ECC verification |
| Power Management | Support the dynamic shutdown of the clock of the main module; Support dynamic frequency conversion in the main clock domain; Supports dynamic regulation in the main voltage domain |
| Peak computing speed | 160GFlops |
| Typical power consumption | 35W@2.5GHz |
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Loongson 3A5000/3B5000 is a general-purpose processor for personal computers, servers and other information fields, based on the LA464 microstructure of LoongArch® autonomous command system, and further increases frequency, reduces power consumption, and optimizes performance. On the basis of maintaining pin compatibility with the Loongson 3A4000 processor, the frequency is increased to 2.5GHz, the power consumption is reduced by more than 30%, and the performance is increased by more than 50%. Loongson 3B5000 supports multiple interconnects based on Loongson 3A5000.
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Last updated 2025-11-04T14:03:47Z
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