Compute Engines
CPU L2 Cache	512 KB per core
CPU Thread Count	2
CPU Instruction Sets	x86-64, AVX-512, AVX-VNNI
Integrated CPU Cores	2x Intel Sunny Cove (IceLake)
Integrated Vector DSP	Cadence Tensilica Vision P6 (512-bit VLIW)
ICE Compute Capability	4096 MACs per cycle
Inference Compute Engine (ICE) Count	12

Core Architecture
Codename	Spring Hill
Die Size	239 mm²
Chip Model	Nervana NNP-I 1150
Transistor Count	8.5 billion
Process Technology	Intel 10nm FinFET CMOS

On-Chip Interfaces
Max Memory Bandwidth	68.25 GB/s
Internal Interconnect	Integrated Ring Bus Architecture
Host Interface Controller	PCIe 3.0 x8
External Memory Controller	Quad-channel LPDDR4X-4266

On-Chip Memory Hierarchy
Deep SRAM	48 MiB Total (4 MiB per ICE) at ~6.8 TB/s
Last Level Cache (LLC)	24 MiB Total (8 cache slices) at ~680 GB/s
Tightly-Coupled Memory (TCM)	3 MiB Total (256 KiB per ICE) at ~68 TB/s

Power and Thermal
TDP (Base)	12 Watt
Power Management Technology	FIVR, DVFS

Chip-Level Features
Peak Performance	50 TOPS (INT8)
Supported Special Data Precisions	FP16, INT8, INT4, INT2, INT1